Frontier tool gets C support

Frontier Design NV's refinement of the A|RT Designer architectural synthesis tool supports a design flow from SystemC or C-language algorithms on toward FPGA implementation. Frontier promises innovative FPGA-oriented optimizations in Version 2.3?announced at the Design Automation and Test Europe conference in Munich, Germany.

A|RT Designer allows design exploration based on manual hardware/software partitioning. Version 2.3 adds enhancements to improve the use of architectural hardware features within FPGAs, a move that is likely to bring the tool into competition with the DK1 design environment for the Handel-C language introduced by Celoxica Ltd.

System C, C++

Whereas DK1 helps engineers develop hardware architectures from the C language augmented by proprietary additions, A|RT Designer works with system-level fixed-point C-language algorithms and has been upgraded to support C++ and the SystemC version of C++.

A|RT technology has been available since 1998 but until now has been more supportive of ASIC design flows. "FPGAs have very special characteristics that have never been adequately addressed by system-level design tools. This is the space we are addressing" with version 2.3, said Frontier CEO Herman Beke.

Though output from A|RT Designer must still be put through FPGA synthesis and place-and-route tools, a number of optimizations should be useful within the relatively fixed structures of FPGAs. They include implementation of registers in lookup-table RAMs, optimization of memory use for nonstandard fixed-point word sizes, single-cycle resource creation and microcode compaction.

A|RT Designer runs under HP-UX, Sun Solaris and Windows NT. It starts at $45,000.

? Peter Clarke

EE Times