Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Using NAND tree test circuits for input parametric testing

Posted: 23 Apr 2001 ?? ?Print Version ?Bookmark and Share

Keywords:american microsystems? ami? input parametric testing? nand tree? asic design?

This application note discusses how to implement a simple NAND tree test structure for input parametric testing of ASIC designs.

View the PDF document for more information.

Article Comments - Using NAND tree test circuits for in...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top