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Silicon prototyping verifies IP functions

Posted: 01 Jun 2001 ?? ?Print Version ?Bookmark and Share

Keywords:ip block? cybershuttle? tsmc? vsia? mim?

SoC design teams face several daunting tasks in optimizing their next-generation products. Since SoC designs can consist of multiple IP blocks, and silicon geometries continue to shrink and designs migrate to lower geometries, approaches are needed to ensure that IP can be transferred from one process geometry to the next, and that IP blocks are efficient and optimized for reuse.

IP developers have realized that they must have a reuse strategy when developing new intellectual property. To effectively implement IP reuse, developers must consider design efficiency, tool efficiency and timely silicon prototyping.

The IP reuse strategy depends upon the initial development approaches of the intellectual property. So design efficiency and the reuse of IP are the first considerations of the developer. The goal is to efficiently design a core that is independent of certain process-geometry tolerances.

Top-down look

To achieve design efficiency, developers often take a modular, top-down approach. This approach allows designers to move from one geometry to the next without changing the architecture.

Because reuse is not a 100 percent automated process, another challenge facing developers is tool efficiency. This becomes extremely important as designs move to the smaller geometries. As geometries shrink to 0.18?m and below, problems surface that affect analog/digital functions, such as signal integrity and crosstalk. Certain tools can address the problems of noise, IR drop, power estimation and other tool-related issues.

Another challenge for IP developers is the need to quickly fabricate silicon prototypes to verify a design in silicon. Until a design is implemented in silicon, the developer is uncertain about his design functionality. Simulations with design tools are necessary first steps, but silicon implementation is the only way to verify final functionality.

Timely silicon prototyping is still an unresolved issue at vertically integrated ASIC providers and integrated device manufacturers (IDMs), since their first priority is producing proven designs for customers, not fabricating test chips.

To overcome this time-to-market dilemma, TSMC has initiated a fast prototyping program called CyberShuttle. CyberShuttle allows IP developers to share a common mask that contains up to 16 different designs. Shuttles are run monthly on a dependable schedule, so developers do not have to wait for months to see their design implemented in silicon.

Signia Technologies, on the other hand, demonstrated in December last year the world's first 0.25?m RFCMOS 2.4GHz Bluetooth radio transceiver IC, and rapidly developed a Bluetooth baseband controller IC employing TSMC's process. Signia's Ulysses SBT-5010 was the first Bluetooth transceiver demonstrated in TSMC's commercially available, volume 0.25?m RFCMOS process. RFCMOS is a high-volume CMOS process for RF devices such as high-Q thick-metal spiral inductors, metal-injection molding (MIM) capacitors, triple-well isolated NMOS transistors, varactor diodes and high sheet-resistance polysilicon resistors. This IC was developed using TSMC's CyberShuttle for rapid development as well as IP for peripheral functions.

Promoting IP reuse

Leveraging third-party alliances provides industry-wide solutions to the challenges of IP reuse and porting to next-generation technologies. It creates an environment that promotes and facilitates silicon IP reuse by making it easier to acquire and integrate IP blocks.

TSMC's Design Service Alliance brings together third-party IP providers, library vendors, EDA tool vendors and chip implementation services. This alliance promotes an environment for each category to come together under one umbrella with one goal-to help make the mutual customer successful. The alliance also allows partners to address industry-wide issues such as IP reuse in a more collaborative environment. For instance, by providing optimized libraries in a certain process, the path for the IP providers to optimize their IP in the same process will be much shorter.

Adherence to standards in development is also a major factor in IP reuse. Recognizing this need, the Virtual Socket Interface Alliance (VSIA) was formed so that representatives from all segments of the SoC industry could work together to solve potential roadblocks with the reuse of IP.

Technical standards allow designers to mix and match and test IP cores, and ease the migration path to lower geometries. To facilitate this mix and match, VSIA specifies open interface standards that allow IP blocks to fit quickly into virtual sockets, both at the functional level and the physical level.

IP deliverables

This approach from VSIA will allow IP developers to produce and maintain a uniform set of IP deliverables, rather than have to support numerous sets of deliverables required for the many unique customer design flows.

Shortening the turnaround time when reusing IP requires access to experienced design support and timely silicon prototyping. By providing IP developers with services that promote quick cycle time and overcome silicon prototyping barriers, design teams will be able to efficiently reuse IP.

? Peyman Kazemkhani

TSMC North America





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