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Extraction method verifies IP functions

Posted: 01 Jun 2001 ?? ?Print Version ?Bookmark and Share

Keywords:verification? ip core? rtl? tuxedo logic? register transfer level?

Keeping pace with the breakneck speed of silicon technology advancement requires substantial manual work. For that reason, verification of the reused custom logic against its original counterpart must be an integral part of the reuse process. Newer, formal methods can both automate the reuse process and ensure identical functional behavior of the core with the original.

In comparing the functional behavior of migrated cores to their originals, companies may choose to write RTL behavioral code in an attempt to mimic the function of the core and then perform a simulation comparison against the corresponding transistor netlist to ensure they perform the same function.

In-house designs

Behavioral models for legacy designs are created based on any internal company knowledge still available. Custom transistor-level designs, typically captured in a schematic format, are difficult to read. Recreating a structured model truly representing the custom design is immediately prone to misinterpretation and therefore to error. The reuse engineer will also use any existing Spice simulations to interpret the in-house custom designs further.

Simulation vectors for the block-level RTL models are designed with the intent of recreating and matching the top-level vectors of the transistor design for the top level of the RTL. Thus, even when simulation comparisons between the behavior model and the transistor design are successful, doubt remains that the two designs are identical, because of the limited set of vectors that are actually applied.

When there is a problem after the integration of all the RTL model blocks, the possibility of misinterpretation can complicate the task of diagnosing the source of RTL modeling errors. Fixing errors in an original custom design mandates correction not only at the transistor level but also at the behavioral level.

Given the headaches of shrinking and reusing full-, semi- or structured-custom cores, some companies choose to migrate some of the blocks to a standard-cell methodology using logic synthesis. Although there is usually some performance penalty associated with moving from a custom design methodology to a logic synthesis methodology that uses off-the-shelf library components, the practice greatly simplifies and automates reuse and retargeting to newer, smaller technologies.

Core reuse is appealing because it theoretically opens the door to creating an entire system with a plug-and-play approach. The availability of ready-made cores, coupled with higher time-to-market pressure, creates a very attractive and compelling reason for core reuse.

For digital circuitry, the use of formal techniques can dramatically accelerate design core creation while assuring the functionality of the intended design for reuse. That holds true either for a custom-based approach for legacy design cores or for a standard-cell-based approach, as in a soft core. Traditionally, ASIC-specific design practices follow a timing-driven design methodology, often requiring the internal knowledge of the design team for effective reuse. Custom migration into different technologies is an area where many companies have begun using formal techniques to automate the core design and reuse process.

It has been proven that custom design conversion and functional integrity for core reuse can be a tedious and iterative process. However, the availability of tools having not only the logic function extraction capabilities but also the verification techniques, as found in the Tuxedo Logic Transistor eXtraction (LTX) software from Verplex Systems, enables the conversion of a custom design with secured functional integrity into a reusable core.

Logic function extraction from a transistor circuit in a Spice netlist eliminates much of user intervention that may have been required in the past. For example, analysis of transistor logic flow direction and identification of weak transistors are completely automated. The algorithms can determine logic function without extensive user input. Boolean function can be extracted from static CMOS, Pass-Gate and tristate logic.

Instead of relying on slow, transistor-level simulation, functional integrity for design reuse can now be accomplished by any number of speedier methods, including higher-level Verilog simulation acceleration (above the transistor level), emulation, or equivalence checking against an RTL behavior model.

Full representation

Having a full representation in an RTL behavioral model as a result of the automatic model extraction process leverages a number of advantages for future reuse, in addition to speeding simulation. Instead of comparing an RTL behavior model simulation against a transistor-level simulation, formal techniques in logic equivalence checking guarantee complete functional coverage of the original design.

Within a single environment, the Tuxedo LEC equivalence checker works together with the extraction capabilities of LTX to automate functional-integrity checking. The transistor-level netlist for the custom design is read into the environment and internally abstracted into a gate functional model, which is used to compare against a behavioral model that may have been externally developed.

Although a custom methodology has many steps, the complete set of features required for such a flow for full RTL-to-transistor-level formal verification now exists to handle those steps automatically. The automated process supports both formal-based and simulation-based flows for effective core array verification.

? Ralph Sanchez

Verplex Systems Inc.

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