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Analog, mixed-signal design flow found wanting

Posted: 16 Jun 2001 ?? ?Print Version ?Bookmark and Share

Keywords:edp? eda tools? ip? reuse?

The analog/mixed-signal design flow has a lot of gaps and is in need of an overhaul, according to the speakers of the Electronic Design Processes (EDP) workshop and the road to a top-down analog design flow will not be an easy one.

Ken Kundert, fellow at Cadence Design Systems Inc., made an appeal for a formal, top-down mixed-signal design process while James Spoto, president of Conexant spin-off Enablix Solutions, called for design platforms and IP that enable RF design. Gary Smith, chief EDA analyst at Dataquest, said the analog design flow is an oxymoron and added that analog designers would not pay for it, even if there was one.

Some relatively encouraging news came from Bill Guthrie, executive VP at Numetrics Management Systems. He said his company's database shows that analog/mixed-signal ICs are designed in less time, with fewer designers, than complex SoCs and that the analog/mixed-signal chips involve more design reuse. However, Guthrie noted that SoC devices are much larger, averaging 4.9 million transistors, against 330,000 transistors for analog/mixed-signal ICs. SoC designs contain only about 0.5 percent analog circuits, averaging 24,000 transistors, Guthrie added. He also noted that analog/mixed-signal circuitry comprise one-fourth of the blocks on a typical SoC.

Kundert said that many analog designers claim they are doing top-down design, when in fact they are not. "They are basically using a bottom-up design style," he said. "They design small blocks at the transistor level, wire them together and hope they work."

The result, Kundert said, is that problems are found too late in the design cycle. "To address time-to-market issues, you need a more formal design process," he said. Such a process, Kundert said, methodically proceeds from the architectural to the transistor level, with each level fully designed before moving down to the next one.

'Pin-accurate' schematic

Kundert's proposed methodology use a "pin-accurate" top-level schematic that serves as a specification for all team members. This schematic, captured before any block design begins, specifies the partitioning into blocks and the interfaces for each block.

Once the schematic is ready, top-level models are written, and verification gets under way. What is needed, is a simulator that can handle behavioral and transistor-level descriptions at the same time.

Kundert said that it is important to have a comprehensive simulation and modeling "plan" that identifies, up front, the problems most likely to be encountered with the design. He said a "chip architect" should coordinate the design process. Such a person should be fluent in a mixed-signal HDL.

Key platforms

Platforms should provide EDA tools, IP component representations and models, a library of parameterized component generators and a comprehensive RF/mixed-signal methodology and flow, said Enablix's James Spoto, who is gearing his company to provide design platforms and associated IP which can reduce R&D efforts by more than half.

However, Dataquest's Smith was blunt. "There is no analog design flow," he said. "Until you have the whole flow, nobody will pay for much." While several vendors allow high-level analog design entry and simulation, there is no real analog synthesis, Smith said. "Analog synthesis should target a library, but most analog synthesis guys are going to basic structures. Until we solve synthesis and DFT-problems, we do not have a solution."

? Richard Goering

EE Times

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