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Startup preps 5Gbps backplane transceiver

Posted: 16 Jun 2001 ?? ?Print Version ?Bookmark and Share

Keywords:backplane transceiver? pam? cmos? multilevel signaling?

In a bid to build a better bit pipe on the backplane, startup Accelerant Networks Inc. is preparing to roll out a proprietary CMOS transceiver that harnesses multilevel signaling technology. Using pulse-amplitude modulation (PAM) technology, Accelerant said that its forthcoming AN5000 transceiver can reach speeds of 5Gbps (10Gbps full-duplex) while maintaining a lower line rate of 2.5GHz.

The technique, which essentially sets four signal levels for each clock cycle, is being used to boost DSL and Ethernet bandwidths. A similar concept is being floated by Rambus Inc. as a fast chip-to-chip signaling technology. By reaching higher speeds with lower line rates, Accelerant claims system designers can increase the interconnect distances and increase densities easier than they otherwise would using existing Serdes, Fibre Channel or Ethernet designs modified for the backplane.

Three eyes

In a presentation, CEO Paul Nahi pointed to a foil showing a simulation of three clean oscilloscope "eyes" separating the four signal levels in one clock cycle. "If you just have Serdes running at 5GHz, you will not have an eye to work with," he said.

Aside from getting more bits per clock, the transceiver has a number of features that make it adaptable to different backplane environments. An adaptive equalizer handles impedance variations that arise from different trace widths and lengths. To do so, it chooses from among 22 million coefficients for each of three taps continuously. With the equalizer, the device will work in any box with trace lengths from 1 to 48 inches, the company said.

The receiver, meanwhile, uses a proprietary algorithm to determine the correct receive levels, then hands that off to the transmitter to eliminate crosstalk from the traces, connectors and vias. To eliminate reflections, the channel is characterized during power-up so that the device can adjust the adaptive equalizer to cancel out reflections.

The chip also has a ninth-order, externally synchronized scrambler that spreads the transmitted data spectrum and eliminates high spectral tones, preventing bit errors. The AN5000 is specified for a bit error rate of 10-22, "so for the lifetime of a box, you will not see one bit's worth of error," Nahi said.

If the system designer later wants to modify the bit error rate or other parameters inside the chip, there is a JTAG port available for remote management. The 0.25-micron AN5000 comes in a standard ball grid array package and is scheduled to be available in sample quantities this quarter. Sample prices will range from $45 to $50. Volume production is slated to begin by the end of the year.

? Anthony Cataldo

EE Times





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