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EDA/IP??

Using formality for RTL-to-gate in LSI Logic's FlexStream design flow

Posted: 24 May 2001 ?? ?Print Version ?Bookmark and Share

Keywords:lsi logic? formality? flexstream? formal verification? verification?

This application note describes procedures and recommendations for using the Formality formal equivalence checking tool for RTL-to-gate equivalence checking.

View the PDF document for more information.



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