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Web site offers open-source TCL scripts

Posted: 07 Jan 2002 ?? ?Print Version ?Bookmark and Share

Keywords:tcl for eda? electronic design automation? design automation? eda? tcl?

Leveraging years of experience writing TCL scripts for electronic design automation tools at IBM Corp. and Synopsys Inc., Alexander Gnusin, a design engineer at Tundra Semiconductor Corp., has launched a "TCL for EDA" Web site where free TCL-based tools and scripts are offered on an open-source basis, along with articles and presentations.

TCL, which stands for Tool Command Language, is widely used for customizing and controlling EDA tools. Usually TCL scripts are written specifically for a given design environment, but Gnusin believes there's an opportunity to document scripts and make them available to others.

"When I worked for IBM, I had to work to make existing tools more convenient," Gnusin said. "When I came out of IBM, I realized that some of my work could apply elsewhere. I want to show people how to use TCL efficiently."

The web site offers both tools and scripts. The main difference of the two, Gnusin said, is that the tools contain a lot more TCL code and are generally independent with respect to the EDA tools they work with.

One of the TCL tools, SynView, provides a graphical user interface for Synopsys' Design Compiler synthesis tool or PrimeTime timing analyzer. Gnusin said SynView includes some features lacking in Synopsys' Design Analyzer product, such as module hierarchy representation, command-entry and script-entry "widgets," wild-card searches for design elements and a netlist viewer that can zero in on regions of interest.

Another TCL tool available at the site, PMAN, is a project-management utility. It helps designers navigate, view and edit Verilog files, and lets them automatically run "lint" checks and synthesize code.

A third tool, Netman, works in Verilog netlists. It provides module extraction, module hierarchy viewing, access to selected module netlist code and a graphical netlist-connectivity viewer for regions of interest. Designers can search for a needed element, such as a port, gate or net, and bring it into the netlist viewer. Then they can explore the region's connectivity.

A tool called "make_top" offers a text-based approach to Verilog structural integration. It generates templates that track the interfaces of all modules that should be instantiated, and allows structural template editing and netlist correction. Gnusin also offers a license monitor tool that tracks available licenses for a specified tool.

Gnusin's TCL scripts are specifically aimed at Synopsys tools, with source code provided. A verification script creates verification wrappers for Verilog modules. Synthesis scripts load Synopsys "db" files, run synthesis, check for correct linkages and look for unexpected latch insertion. Timing scripts print maximum-slack reports for input and output ports. Testability scripts can insert scannable flip-flops and replace non-scannable registers with scannable ones.

The site also includes some papers and a presentation by Gnusin, who has promised to continually update the site with new scripts and articles. He is asking viewers for feedback and scripting ideas.

Richard Goering

EE Times

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