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Aldec rolls out fast, fully automated FPGA design verification tool

Posted: 10 Jan 2002 ?? ?Print Version ?Bookmark and Share

Keywords:aldec? fpga design tool? design tool? design verification? formal verification tool?

Claimed to be the fastest, most fully automated FPGA design verification tool, Active-HDL 5.1 addresses the latest design trends in the EDA industry, the company says. The tool was developed to provide support for system designers working on high-density FPGAs, as well as design teams working on collaborative multi-million-gate FPGA designs.

The tool's multi-language simulator, which allows for concurrent simulation of VHDL, Verilog and EDIF designs, has been enhanced, offering a universal and fast design verification platform. Active-HDL also makes full use of the memory, allowing very complex designs to be handled in a PC environment.

Providing increased productivity, the design tool's features include: I/O port conversion in the Block Diagram Editor, which eliminates the need for the intermediary step that converts binary code to VHDL statements; graphical processes that allow VHDL "processes" and Verilog "always" statements to be placed directly on the block diagram; post-simulation debug, which saves a full history of simulation results so that designers can analyze simulation results in detail at a later time; and job control, which allows designers to run design portions of the design in parallel, speeding the design cycle.

Active-HDL 5.1 also offers licensing flexibility because designers may have the license ascribed to a USB port in place of a traditional parallel port or floating license.

The Active-HDL environment is currently offered with either a floating or node-lock license and includes Aldec's HDL Project Manager, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation.





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