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EZchip samples 10Gb, seven-layer packet processor

Posted: 10 Jan 2002 ?? ?Print Version ?Bookmark and Share

Keywords:ezchip technologies? ezchip? packet processor? processor? network processor?

EZchip Technologies has announced tapeout and sampling of a 10Gbps, single-chip packet processor that allows fully programmable packet classification, modification, forwarding and policing at full-duplex wire speed.

The processor, dubbed the NP-1, is an OC-192, seven-layer device designed to answer burgeoning demand for low-power, high-density line cards. It is designed to operate with EZchip's soon-to-be-announced QX-1 device, which is a single-chip, 10Gbps, OC-192 traffic manager.

To meet the demands of seven-layer packet processing at 10Gbps rates, the NP-1 processor incorporates the company's proprietary TOPcore pipelined parallel-processing architecture, on-board search engines and patented hashing algorithms for field data extraction to enable content-aware processing.

Content-aware processing allows Layer 2 to Layer 4 switching and routing with granular flow classification, and Layer 5 to Layer 7 deep-packet processing for content switching, Transmission Control Protocol offloading, security and traffic analysis. A 10Gb or 1Gb Ethernet MAC is also included on-chip.

"Most NPUs [network-processing units] to date are based on off-the-shelf RISC processors, which cannot scale to the requirements of 10Gb network processing," said Eli Fruchter, president and CEO of EZChip, a subsidiary of LanOptics Ltd based in Migdal Heimek, Israel. "Instead, we've based our NP-1 on our own Task Optimized Processors [TOPs], which are optimized specifically for packet processing at these rates."

The TOPcore architecture actually comprises four separate TOPs processors, one each for packet modification, resolution, searching and parsing. Proprietary hashing algorithms ensure that searches are 100 percent predictable, said Fruchter. "Others have collisions 20 percent of the time. Our patented algorithms guarantee a solution in two clocks," he said.

The processors are pipelined such that each packet goes through each processor, and the processors are replicated "tens of times" on the NP-1, Fruchter said, without giving the exact replication count.

A key point of the architecture's design is that a customer is oblivious to the actual number of processors on board. "They only have to program for one, and then an on-board scheduler takes care of the processing," Fruchter said.

Wide memory buses

To integrate the search engines on board, EZChip had to embed up to 5MB of DRAM on the chip using 256- to 512-bit-wide memory buses to reach the access speeds required at 10Gbps rates. The size of the buses as well as the amount of on-board memory place the device on the leading edge of processor development, according to the company.

Available development tools include Ezdesign, Ezdriver and evaluation boards. Ezdesign includes a simulator, compiler, debugging facilities, and traffic and database generators. An applications library provides reference code for implementing various applications such as Layer 2 switching, multiprotocol label switching, Internet Protocol routing, network address translation and URL-based server load balancing.

The processor is manufactured in partnership with IBM Corp., using IBM's 0.185m process. The company also uses IBM's ceramic-column grid-array packaging technology to place the complete device on a 15W, 1,247-pin chip.

Sampling will begin in March, with plans afoot to eventually migrate to IBM's 0.115m process. The evaluation boards are available with a choice of Gigabit Ethernet, 10Gb Ethernet and OC-192 packet-over-SONET interfaces.

Patrick Mannion

EE Times

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