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Xilinx axes analog to cool CPLD power consumption

Posted: 16 Jan 2002 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? cpld? complex programmable logic device? complex pld? pld?

Are CPLDs in their current form about to reach the end of the road? Xilinx Inc. believes that they are, and says the only way to keep scaling them linearly is to get rid of their power-hungry analog circuitry once and for all.

To that end, the San Jose, California-based PLD vendor is rolling out its latest all-digital CPLD based on its Coolrunner low-power technology. Dubbed Coolrunner-II, the new family is capable of operating at up to 300MHz but consumes <1005A of active current.

Based on those power and performance specs, Xilinx considers the introduction of the Coolrunner-II no less significant than Altera Corp.'s first CPLD in the 1980s and Lattice Semiconductor Corp.'s development of the ISP CPLD years later.

"We believe that the standard CPLD is going to hit the wall and that we are in fact leaders of a new trend in the industry," said Willem Roelandts, Xilinx's president and CEO. "We don't think people are going to be able to build deep-submicron CPLDs with sense amplifiers."

According to Xilinx, the relative performance of conventional CPLD technology levels off at the 2.5V operating-voltage level and then starts to decline at 1.8V. The culprit, according to the company, is the sense amplifier, which is at the heart of conventional CPLD product terms.

"Sense amplifier technology doesn't scale well in the product term array," said senior marketing manager Steve Sharp. "When you close the voltage window you don't have as much range for that amplifier to operate in, so you have to crank up the current to get effective switching. When going from 3.3V to 2.5V, you actually have to pump more current because you have a smaller region to switch in.

"When you get to 1.5V, there's nothing left between the n- and p-channel thresholds."

By keeping the CPLD design all-digital, Xilinx says it can get reduced voltage and lower current while continuing to scale performance in a linear fashion. A 128-macrocell device with eight 16-bit counters running at 50MHz, for example, dissipates just 10mW in active mode and 1805W in standby.

Xilinx's yet-to-be released 32-macrocell XC2C32 device boasts a best-case pin-to-pin delay of 3.5ns and runs at 303MHz. And its high-density, 512-macrocell XC2C512, which is scheduled to hit the market in early 2002, has a 6ns delay while running at 189MHz.

Using 0.185m design rules, the Coolrunner-II devices operate using a core voltage of 1.8V and can tolerate 1.5, 1.8, 2.5 and 3.3V I/Os. The wide I/O voltage tolerance means the family can support more I/O standards than previous CPLDs from Xilinx. Among them are LVTTL, LVCMOS, HSTL and SSTL.

For analog interfaces, the devices include Schmitt trigger inputs, also called hysteresis, to provide noise immunity and for making simple oscillator circuits. The devices also include a programmable on/off switch. "This allows you to switch off an input without toggling the whole array, saving power," Sharp said. "An analogy is putting tristate buffers outside to keep the inputs from toggling."

As for clock management, the family allows a clock to be doubled or divided at each macrocell. One way to reduce power while maintaining performance, for example, would be to divide a global clock in half and then double it at the macrocell's output, Sharp said.

Xilinx has also added better security features in its new CPLD family. Coolrunner-II has four levels of design security buried within the layers of the device and scattered throughout the die to deter detection. Software design tools for HDL synthesis, Abel simulation and a fitter for evaluation are available free from Xilinx's web site. In addition, Xilinx is offering a separate integrated software environment tool series for timing closure that can be integrated with other electronic design automation tools.

The Coolrunner-II family can be delivered in chip-scale, surface-mount and high-performance BGA packages. The 64-macrocell XC2C64 is available today, and the five other Coolrunner-II family members are scheduled to roll out in the first half of 2002.

Anthony Cataldo

EE Times





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