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Maxim serializer converts 622Mbps parallel data to 2.5Gbps serial data

Posted: 16 Jan 2002 ?? ?Print Version ?Bookmark and Share

Keywords:maxim? maxim integrated products? serializer? deserializer? communications ic?

The MAX3892 3.3V, 2.5Gbps/2.7Gbps 4:1 serializer with clock synthesis and LVDS inputs is suitable for converting 4-bit-wide 622Mbps parallel data to 2.5Gbps serial data in DWDM and SDH/SONET applications.

Operating from a single 3.3V supply, the serializer accepts 622Mbps LVDS parallel data inputs and delivers differential CML serial data and clock outputs while consuming only 455mW. A 4-bit-by-4-bit FIFO allows for any static delay between the parallel input clock and the internally synthesized clock. Delay variation up to a unit interval is allowed over temperature. A fully integrated PLL synthesizes an internal 2.5GHz serial clock from a 622.08, 155.52, 77.76 or 38.88MHz reference clock. A selectable dual VCO allows high jitter performance of 1.3ps at both SONET and FEC data rates. A loopback data output is provided to facilitate system diagnostic testing.

It forms a complete two-chip 2.5Gbps/2.7Gbps transceiver solution when used with the MAX3882 1:4 deserializer with clock recovery circuits.

The MAX3892, in a 44-pin QFN, is specified for the extended temperature range of -400C to 850C. Pricing is at $31.63 in quantities of 1,000.





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