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R&D consortium eyes system-in-package substrates

Posted: 22 Jan 2002 ?? ?Print Version ?Bookmark and Share

Keywords:system-in-package device? material? multiple chip? single package? insulator film?

Five Japanese companies have formed an R&D association to develop materials and technologies for high-density substrates that will be used in system-in-package devices, which store multiple chips in a single package.

"Materials for print wiring boards are reaching the limit. We want to break this bottleneck and develop new materials," said Akishi Nakaso of Hitachi Chemical Co. Ltd, acting project leader of the association, named the Technology Research Association for Advanced Jisso Functional Materials.

Formed to conduct the five-year project, the association is subsidized by the New Energy & Industrial Technology Development Organization (NEDO), which is under the jurisdiction of the Japan's Ministry of Economy, Trade and Industry. NEDO will provide about $2.2 million for the current fiscal year, and as much as $20 million over five years. Association members are Sumitomo Bakelite, Hitachi Chemical, Toray Industries, Shinko Electric and Toray Research Center.

Each of the member companies and six Japanese universities will cooperate on the development of substrate technologies that are expected to be needed in the 2008-2009 time frame. They include interlayer insulator films of low and high dielectric constants, processes capable of forming fine wiring patterns able to transmit GHz-level signals, and passive component interconnect technologies.

Yoshiko Hara

EE Times





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