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Toshiba 32-bit processor targeted at automotive displays

Posted: 23 Jan 2002 ?? ?Print Version ?Bookmark and Share

Keywords:toshiba america electronic components? taec? toshiba? microcontroller? embedded cpu?

The TMPR3916F 32-bit MIPS-based microprocessor integrates a dedicated graphics display controller, memory controller and CAN modules to enable compact, cost-optimized system solutions with improved graphics performance. The 208-pin QFP device is targeted at automotive information display applications such as instrument clusters, dashboard graphics and navigation systems.

The TMPR3916F features a single external DRAM in a x32 configuration that supplies all necessary graphics buffer and main memory. The unified memory architecture provides the CPU with direct access to the display memory for drawing and rendering functions.

The chip's integrated memory controller consists of an SDRAM controller and the memory controller for SRAM, ROM and Flash memory. The graphics display controller features four-layer overlay hardware processing with transparent color, and has a 16-bit color palette of 544 colors.

The CAN-bus controller is fully compliant with the CAN 2.0B standard and has two channels with 16 mailboxes each. It operates at speeds up to 1Mbps, ensuring compatibility in both 11-bit standard frame and 19-bit extended frame identifiers.

Other peripheral controllers include a two-channel DMA controller, an interrupt controller with three external interrupts and one non-maskable interrupt, serial I/O controllers, and a one-channel timer.

Manufactured using the 0.355m CMOS process, the TMPR3916F measures 28-by-28mm with a 0.5mm pitch. It operates at 60MHz with a 3.3V power supply and 5V-tolerant I/O, and a maximum power dissipation of 1.2W. The device has an operating temperature range of -400C to 850C. Its RISC core is based on the MIPS R3000A architecture, and has an on-chip instruction cache of 4KB and data cache of 1KB.

The TMPR3916F is quoted at $20 each in quantities of 10,000.





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