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Zarlink chip packs three PLLs to reduce signal wander

Posted: 25 Jan 2002 ?? ?Print Version ?Bookmark and Share

Keywords:zarlink semiconductor? zarlink? pll? phase locked loop?

The company has incorporated three independent PLL chips within a single IC, enabling the device to reduce signal wandera cyclical variation in signal frequency that is a prime cause of data errors in SONET and SDH communication networks. The chip also provides for timing transients and features a holdover accuracy of 0.1ppb.

The device is claimed to be the industry's first off-the-shelf SONET/SDH digital PLL to fully meet the synchronization requirements of Telcordia's GR-1244-CORE and GR-253-CORE standards for SONET Stratum 3E clocks, and the ITU's G.812 requirements for SDH Type I clocks.

The chip can be used on timing cards and line cards in SONET/SDH add/drop multiplexers and uplinks, terminal multiplexers, IADs, and ATM edge switches. The chip also provides multiple clocks for legacy PDH equipment, and generates timing for CompactPCI, ST-BUS and GCI backplanes.

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