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Toshiba, Samsung show 1Gb Flash designs

Posted: 07 Feb 2002 ?? ?Print Version ?Bookmark and Share

Keywords:toshiba? samsung electronics? samsung? flash memory? flash?

Serial Flash reached the gigabit density at the International Solid-State Circuits Conference, where Toshiba Corp. and Samsung Electronics Co. Ltd each described 1Gb NAND Flash designs on Monday (Feb. 4).

Both companies based their designs on 0.135m process technology, which is now coming into widespread use for memory manufacturing. Neither said when commercial production of their respective devices would begin.

Such devices, mounted one on each side of a typical memory card used in a digital still camera or portable audio system, would provide 256MB of storage.

Samsung engineer Jun Lee described his company's 32-bank design with a center-placed row decoder that supports a 1KB option. With a 2KB page size, the program throughput is rated at 7MBps. That provides a 75 percent improvement in the time needed by previous NAND Flash to program unwieldy 512KB pages, Lee said.

Read throughput is 16MBps in by-8 mode and 27MBps in the by-16 configuration. The cycle time is 50ns at 1.8V operation.

"Voice and moving-image storage requires a very high programming speed, but in high-density devices the charge pump is hard to scale down. We have to use a 20V charge pump even for these low-voltage devices," Lee said.

Samsung's design is based on a 1.8Vdd, and the company's engineers developed a new charge pump based on a series of diodes to boost the 1.8V to 20V for programming. Samsung created the diodes from the typical PMOS transistors used in the CMOS process.

Samsung also employed a programming cache that enables the next page data to load while the current page mode is in operation. While Lee did not reveal the die size, he said the cell size is 76nm2 on a 0.125m process.

Toshiba design manager Ken Takeuchi said the area efficiency of Toshiba's 1Gb is double that of the company's 512Mb NAND Flash, with a cell size of 77nm2 and a die size of 125mm2 on a 130nm process. The chip operates on a 2.7V supply.

Toshiba implemented a write cache architecture that supports a 10.6MBps fast programming time, and a 20MBps read time, supported by a cache read function. The page size can vary from 512KB down to 2KB.

While cell programming normally requires four cycles of 50ns each, or 200ns, Takeuchi said that most cells can be programmed in three cycles. "Only a very small portion of the programs take four cycles," he said.

David Lammers

EE Times

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