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Interworks offers solution for Agere's Payload Plus chipset

Posted: 08 Feb 2002 ?? ?Print Version ?Bookmark and Share

Keywords:interworks? agere systems? agere? payload plus? memory chips?

Interworks has offered a memory partitioning solution for Agere's 2.5G Payload Plus network processor chipset, an approach claimed to ease space constraints, add flexibility and reduce development time for the chipset.

The traditional memory design for the Payload Plus chipset requires high-speed memory modules for the routing switch processor (RSP), the fast pattern processor (FPP) and the Agere system interface (ASI). Interworks' solution repositions most of these components onto a memory daughter card mounted in parallel to the system board.

Agere's Payload Plus is an OC-48c network processor solution that performs all of the classification, policing, traffic management, QoS/CoS, traffic shaping and packet modification functions needed for a carrier class network platform.

Memory densities for the FPP range from 4MB to 16MB of SRAM for the program section, 4MB to 16MB of SRAM for the control section and 32MB to 128MB of SDRAM for the Data Buffer section. Densities for the RSP range from 4MB to 16MB of SRAM for the link List, 8MB to 32MB of SRAM for the scheduler and 64MB to 256MB of SDRAM for the data buffer section.

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