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TI unveils 90nm process technology

Posted: 08 Feb 2002 ?? ?Print Version ?Bookmark and Share

Keywords:texas instruments? ti? transistor? chip-level multiprocessing? prototypes?

Texas Instruments Inc. has unveiled its 90nm (0.095m) process technology, which will support transistor densities that allow chip-level multiprocessing, and require several techniques to manage power consumption.

"This is an evolutionary kind of change from the process we used at 130nm. But as you make the transistors that much smaller, it becomes more difficult," said Hans Stork, director of silicon technology research at TI here. One major change will be the extensive use of 193-nm lithographic tools with phase-shift masks; another will be introduction of an intermetal-level dielectric, with a k-value of 2.8, said Stork.

TI expects to offer prototypes of chips based on the new process by the first quarter of next year, and to qualify the process for mass production in the third quarter of 2003.

"Basically, we are on a two-year schedule to go from one process generation to the next," said Peter Rickert, a TI fellow. TI is now starting to ship significant quantities of 130nm (0.135m) silicon in the form of its C6 digital signal processors, with some 25 designs moving into production in the coming months. Mass production at the 90nm rules in 2004 and beyond would utilize DM0S6, the 300mm fabrication facility TI is now outfitting in Dallas.

TI's 90nm "platform"?including design tools, libraries, and process technology?carries some predictable benefits: transistor densities will roughly double from the 130nm generation, and transistor peak performance will improve.

At 90nm design rules, about 400 million transistors can be placed on the largest manufacturable die, and roughly 200 million can be placed on a typically-sized die.

Performance also will receive the expected boost. TI's fastest DSPs produced in a 130nm process are rated at roughly 600MHz; the 90nm generation will see DSPs that can run about 25 percent faster.

Rein on power

The higher transistor count and frequencies result in higher power consumption, following the familiar formula that power consumption equals the capacitance times the square of the voltage, multiplied by the frequency (P=CV2F).

"The core operating voltage drops to 1.1V, compared with 1.2V for the 130nm node. At 90 nanometers we will offer 1V for low-power applications like 2G phones, or an overdrive mode at 1.2V, depending on how designers want to trade off performance and power," said Bob Pitts, a senior member of the technical staff on TI's 90nm development team.

Voltage scaling provides some relief from the onrushing train of rising power consumption. Combined with the smaller capacitance of the scaled-down transistors, per-gate power consumption will drop from 10.75m/GHz per gate (for the 130nm transistors with a Vdd of 1.2V) to 5.255W/GHz per gate at the 90nm node with a 1.1V power supply.

Nevertheless, the limited thermal budget for many systems, and packaging issues will make power the chief issue at the 90nm node. That will lead designers toward more chip-level multiprocessing, deeper pipelining, and memory blocks that can be powered down while retaining state, Pitts said.

On-chip multiprocessing within SoC designs will become more commonplace, along with massive amounts of on-chip memory. A recent chip designed for VoIP phones included six DSPs on board, Rickert noted; that kind of chip-level multiprocessing will become more common at the 90nm node, he said.

Keith Diefendorff, vice president for product strategy at MIPS Technologies Inc., said the 90nm node will usher in widespread use of 64-bit processing. In many cases designers will opt to use lower clock frequencies in multiprocessing designs. Many designers will use "parallel circuits at frequencies that keep power down. Then, when you need more performance, the frequency can be increased just for the period of time that you have more work to do.

Oodles of transistors

Indeed, 200-million transistor budgets will practically mandate SoC designs, many of them based on 64-bit processing engines. "At the kind of transistor budgets possible at 90nm, who really cares how many transistors a 64-bit ALU will take?," said Diefendorff. "The cost of 64 bits is immaterial if the system-level gains are there" for streaming media, security, and other applications. Earlier in his career, Diefendorff designed microprocessors at Motorola Inc. and Advanced Micro Devices Inc. He also edited Microprocessor Report for a time.

TI will offer different gate lengths for standard (60nm Lg), low-power (70nm), and high-performance (37nm) applications. The most aggressive gate length, 37nm, will be combined with a 13-angstrom gate oxide in a high-performance version of the 90nm process, which Sun Microsystems Inc. will use for its Ultrasparc V processor.

Sue Kuntz, a technology strategist at Sun's high-performance computing group, said, "Power and power density are the major issues facing us at the 90nm node. Moore's Law is Moore's Law, but it doesn't tell you anything about what to do for power consumption."

In part to save power at the 90nm node, high-performance MPUs will turn to thread-level processing, as a complement to the instruction-level processing that has dominated computing architectures thus far, she said.

In an effort to prevent leaky circuits and to conserve power during standby mode, TI will introduce back biasing at the 90nm node, using a transistor's body effect to increase the effective threshold voltage (Vt). Pitts said the effective Vt can be increased by applying a bias larger than the power rail to the transistor's well, the p-substrate for the nMOS or the n-well for the pMOS.

TI is also investigating techniques which apply a voltage higher than Vdd to the n-well to raise the effective threshold voltage of the pMOS transistors.

Rather than apply a negative voltage to the substrate, an alternative method is being considered to back bias the nMOS transistors. An equivalent higher effective Vt for the nMOS can be accomplished by leaving the p-substrate at ground while raising the voltage of the transistors.

"This technique allows circuits to be power optimized by applying the higher well voltage during standby and the normal well voltage during normal operating conditions. Other techniques, such as simply lowering Vdd during standby operation, are independently or simultaneously applied to the circuits, as well," Pitts said.

SRAM will continue to be the memory of choice at TI in the 90-nm generation, largely because it uses the same standard process and keeps processing costs low. Stork said TI is working with Ramtron Inc. on ferroelectric RAM development, but it is too early to say whether that technology will become available for the 90nm node.

TI is claiming that its 6T SRAM design has the smallest cell size among its competitors, many of which reported their SRAM cell size for the 90-nm node at the recent International Electron Devices Meeting (IEDM) in Washington. For L2 cache, TI's cell size is 1.14 square microns, which compares well with IBM's reported 6T cell size of 1.21 square microns, Rickert said.

For higher performance L1 cache, the cell is stretched in one dimension to 1.48 square microns.

TI will offer up to 30Mb to 40Mb of SRAM on designs at the 90nm node, which compares with a maximum of 24Mb at the 130nm node, Rickert said.

? David Lammers

EE Times





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