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Infineon samples low-latency DRAMs aimed at networking

Posted: 12 Feb 2002 ?? ?Print Version ?Bookmark and Share

Keywords:infineon technologies? infineon? memory chips? memory? dynamic random access memory?

Signaling its readiness to fight for the networking market, Infineon Technologies AG said it would start sampling its flavor of low-latency DRAM chips Monday (Feb. 11). The debut of the German chip maker's RL ("reduced-latency") DRAM pits Infineon against Fujitsu Ltd and Toshiba Corp. in a battle over memories suitable for high-speed networking equipment.

The reduced-latency DRAMs will ship in 256Mb densities and initially clock in at 200MHz. Later versions will run at 250MHz and 300MHz, Infineon managers said, supporting 600Mb per pin per second and an optimum bandwidth of 2.4Gbps. Random access is offered in each of the eight banks and row cycle times are as low as 25ns!about half that of standard DRAM.

The chips will eventually find their way into servers and routers as well as Level 3 cache memory, where SRAM will start to lose its dominance as system designers look for cheaper, denser alternatives with similar performance.

So far, this new crop of low-latency DRAMs looks to have an edge over graphics RAM or Rambus DRAM as the SRAM replacement. Yet the developing market has already splintered into two camps: Fujitsu/Toshiba vs. Infineon and Micron Technology Inc. Micron licensed the RL-DRAM technology from Infineon and plans to release its 256Mb samples in about a month.

Fujitsu has dubbed its low-latency contender fast-cycle RAM and it, too, is sampling parts. Others also look ready to enter the market. Fujitsu is partnering with Toshiba on the development of FCRAMs. Both companies will sell compatible parts independently.

Samsung Electronics has said it will either license a version of the new DRAM variant or put a design of its own up for consideration, while Elpida Memory Inc. has also indicated its desire to compete.

Despite the early fragmentation, the market for low-latency DRAMs isn't expected to rev up until next year, when volume production begins. The stakes will be high as suppliers look to land socket space in network designs that would likely result in lucrative long-term supply contracts and offer memory makers a more specialized alternative to commodity DRAM.

Infineon believes its parts will have an advantage over FCRAM, graphics RAM or Rambus as network speeds increase from 1Gbps to 10Gbps (OC-192) and on up to 40Gbps (OC-768).

RL-DRAM is offered in two organizations!8Mword-by-32 and 16Mword-by-16!with the latter providing greater flexibility to scale upward, said Martin Peisl, senior director of specialty DRAM marketing for Infineon.

Graphics DRAM also has a x32 organization, currently goes to 300MHz and is scalable, ostensibly making it a contender. But Peisl said it's not likely to claim design wins. Although the I/O is similar, graphics RAM is still page-mode oriented, he said, to allow graphics processors to take advantage of raw bandwidth!the pin speed and the page speed!to chew through linear data.

"The networking people cannot do that," Peisl said. "They have a fixed packet size and the next packet that is coming in has to be processed within 25ns or 40ns, and so you need random access. The raw random bandwidth of a graphics RAM is about half that of RL-DRAM."

As for Rambus, Peisl called its higher latency and lower bus performance when doing random access a "luxury" that network processors can't afford.

The 200MHz RL-DRAM samples will come in 144-ball thin, FPBGAs and carry a $54 price tag. The chips will move into mass production in the third quarter.

Infineon is already working on its next generation of low-latency parts, which will move to a 110nm process and scale to 400MHz as a baseline, with a 20ns row cycle time. Sampling is to start in the first quarter of 2003.

Mike Clendenin

EE Times





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