Altera tweaks TSMC high-density PLD process

Altera Corp. has started providing samples of its highest-density logic device based on the latest 0.135m design rules. To make the transition, the PLD vendor worked closely with foundry partner TSMC on a special process to boost device density while maintaining performance and keeping power consumption under control.

With 70,000 logic elements and 1.1MB of embedded RAM, the Apex 2 EP2A70 is Altera's highest-density device to date and the first to exploit 0.135m design rules.

Some of the early customers of the devicesuch as Rockwell Collins Inc.are considering using it as a prototyping vehicle that can be converted by Altera into less expensive mask-programmable devices for high-volume production, according to Altera.

For the 0.135m technology node, TSMC has come up with four standard process modules, which vary by core voltage, gate dielectric oxide thickness, transistor threshold voltages, metal pitch and other factors. However, Altera's EP2A70 uses a specialized 1.5V overdrive option for a transistor initially designed for 1.2V operation.

Altera chose this route to get the optimal transistor performance while keeping leakage current under control.

Subthreshold leakage

Today, the main source of leakage current is subthreshold leakage, also known as off-state leakage, which is caused by current flowing beneath the surface of a transistor's source/drain channel. To counter this effect, chip manufacturers can tune a device for a higher operating voltage. In this case, Altera chose the 1.5V core voltage instead of the standard 1.2V offering.

Normally, the 1.5V core voltage option from TSMC is used for a low-power transistor with a relatively thick gate oxide to further reduce leakage current. However, Altera chose to stick with a thinner 20-angstrom gate oxideapproximately six atomic layers thickas a way to improve transistor performance. In reality, the gate oxide is electrically equivalent to 28 angstroms because of the effects of depletion, said Francois Gregoire, vice president of technology at Altera. But it is still physically 6 angstroms thinner than the gate oxide used in the standard 1.5V option from TSMC.

In this way, Altera said it can get lower subthreshold leakage and faster transistor switching speeds than it otherwise could. This was not a hard choice to make because subthreshold leakage is a bigger concern than gate leakage, which gets worse as the gate oxide gets thinner with each process technology node. But gate leakage is also starting to raise eyebrows.

"We found that 20 angstroms was the best trade-off between leakage and performance," Gregoire said. "Gate leakage is still much lower than the I-off, but it will become significant at 0.15m. Every 2 angstroms of thinning multiplies gate leakage by approximately 10 times. So when 20 angstrom on 0.135m goes to 16 angstroms or 15 angstroms on 0.15m, it gets multiplied by a factor of 100." Therefore, he said, "At 0.15m we will need some new techniques."

Altera also tweaked the process by fattening some of the top-layer copper wires as a way to reduce the resistance. These top metal layers use looser design rules because of process constraints. In addition, the critical speed paths tend to use wider spacing to minimize parasitic capacitance. To improve metal pitch, Altera plans to move from eight to nine metal layers for its next-generation 0.135m products.

"If you need to increase pitch, you either build wider or taller," Gregoire said. "When you go wider, there is an impact on die cost, so it is much better to build taller. It's slightly higher in cost per wafer, but the yield is better."

Yields should improve further when Altera moves its designs to 300mm wafers, as it expects to do in Q2 of this year, Gregoire said.

? Anthony Cataldo

EE Times