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Xyron offers fresh approach to solve processor latency

Posted: 19 Feb 2002 ?? ?Print Version ?Bookmark and Share

Keywords:startup intellectual property house? xyron semiconductor? microprocessor? rtos hardware? cpu?

Startup IP house Xyron Semiconductor this week will describe a technology that uses SRAM bits to take care of some of the more mundane tasks that tend to slow down a processor's performance, EE Times has learned.

Hoping to sell its technology to microprocessor vendors, Xyron believes processor designers are better off throwing more hardware at task switching and interrupt scheduling in the same way that an executive can get more done with the help of a secretary. Rather than being handled in software, internal and external interrupts are directed to the RTOS hardware.

By having this hardware mechanism built into a CPU, the latency normally associated with these tasks are taken out of the picture, allowing a CPU to spend its time doing more useful things like decoding audio and video algorithms, the company said.

"This is a back-to-basics approach that frees up the processor to do processing," said Len Elias, Xyron's director of marketing. This week, the company will detail its technology and demonstrate how a 13MHz microprocessor embedded into a Xilinx FPGA can switch between eight different tasks.

"You essentially get to switch between the tasks with zero overhead," Elias added. "One example could be to develop a cell phone with baseband processors that can do 802.11, and then change it back to a cell phone with a general purpose processor and then switch to Bluetooth."

The intellectual property that Xyron will try to license to CPU vendors is not a coprocessor that can be bolted on the side; it would have to be integrated into the very fabric of the chip's architecture. And it's not architecture specific, so it's just as suitable for a digital signal processor as it is a general purpose RISC design.

The register issue

Processor designers often add more registers to their architectures to overcome interrupts and task switching. But Xyron says the problem with this approach is that this increases wiring and capacitance-related delays, a situation that is only getting worst now that interconnect has become the main culprit holding back logic performance.

Plus, registers take up more silicon real estate than do SRAMs, which can be used to store hundreds of tasks that need to be handled at any given time. Elias said Xyron's task and interrupt management mechanism will increase the die size anywhere from 15 to 25 percent, but that the system would end up costing less because it could do without expensive co-processors.

The company has so far not disclosed its technology in full, but a U.S. patent by the company describes a way to use one or more auxiliary latches to swap data between memory and registers. The mechanism swaps connections between alternate running registers and the auxiliary registers while transferring other tasks to and from storage memory. Another feature of the invention is an "impatience" counter, which gives more priority to tasks as their deadline approaches.

Xyron was founded in 1996 by CEO John Peers and chief scientist Brian Donovan, who developed the technology. The company plans to sell its IP to MPU makers and will later this year introduce its own processor to the merchant market. The company now has 20 employees, and has raised $2 million in venture capital funding.

? Anthony Cataldo

EE Times

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