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Altera PLDs offer three times more memory

Posted: 26 Feb 2002 ?? ?Print Version ?Bookmark and Share

Keywords:altera? pld? programmable logic device? dsp? digital signal processor?

Designed using the company's TriMatrix memory structure, the new line of Stratix PLDs from Altera offers up to 10Mb of RAM and 1,650 embedded memory blocksclaimed to be three times more than any other device.

The TriMatrix memory structure consists of the MegaRAM, M512, and M4K blocks. The MegaRAM offers up to 12 blocks, each with 512Kb. The PLD is suitable for IP packet buffering, system cache, video frame buffers, and processor code storage.

The M512 has up to 1,118 small memory blocks, each with 512 bits, making it suitable for clock domain buffering, DSP shift registers, general purpose FIFO, and FIR filter delay lines. The M4K offers 4Kb each for up to 520 utility blocks. The MK4 is used for ATM cell packet processing, header/cell storage, channelized functions, program memory for processors.

All the memory blocks include extra parity bits for error control, embedded shift register functionality, mixed width mode, and mixed clock mode support. In addition, the M4K and MegaRAM blocks support true dual-port mode and byte masking for advanced write operations.

The Stratix PLDs are based on a 1.5V, 0.13?m all-layer copper SRAM process, with densities ranging from 10,570 to 114,140 logic elements. They offer up to 28 DSP blocks with up to 224 embedded multipliers, suitable for DSP applications that require high data processing.

The PLDs extend support to LVDS, LVPECL, PCML, and HyperTransport, as well as high-speed interfaces, including UTOPIA IV, SPI-4 Phase 2, SFI-4, 10Gb Ethernet XSBI, and RapidIO. The Stratix devices also integrate a hierarchical clock structure and up to 12 PLLs.





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