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Synopsys Verilog, VHDL simulator improves performance

Posted: 28 Feb 2002 ?? ?Print Version ?Bookmark and Share

Keywords:synopsys? ic design? vhdl tool? verilog hdl tool? vhdl simulator?

The company has announced the release of the VCS 6.1 Verilog simulator and the Scirocco 2001.10 VHDL simulator, which are claimed to improve RTL and gate-level simulation performance by up to three times over previous versions.

Incorporating cross-compile technology, the 64-bit VCS is also claimed to reduce memory consumption by up to 30 percent in Verilog designs, and accommodates simulated designs in excess of 20 million gates within existing verification environments.

Cross-compiling allows users to compile large designs on 64-bit servers, and then simulate the designs using 32-bit workstations. Using this flow, customers utilize the 64-bit machines' capacity for the one-time, memory-intensive compile step, while enabling engineers to utilize their existing hardware and Verilog PLI-based software investments for simulation.

VCS 6.1 supports the Verilog 2001 language, as well as the Verilog Programming Language Interface and the Verilog Programming Interface library.

The Scirocco 2001.10 is claimed to have an improved "out-of-the-box" event-based performance up to three times without user intervention. It also features expanded cycle-based performance for both non-RTL blocks and memories described with the VITAL VHDL ASIC library design standard.

Pricing for the VCS 6.1 and the Scirocco 2001.10 both start at $20,250 for a one-year technology subscription license (TSL). The VCS MX package for mixed-HDL simulation starts at $31,500 for a one-year TSL.

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