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Physical synthesis for complex FPGAs

Posted: 01 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:pld? fpga? cpld? lvds? lvcmos?

While FPGAs continue to get bigger, the time-to-market window only seems to get smaller. With FPGAs at more than 10 million system gates today and FPGA vendors forecasting 50 million gates by 2005, designers face new engineering challenges in order to optimize these devices and still meet their narrow market windows. Additionally, IP is increasingly being used in today's multi-million gate FPGAs.

These emerging "mega-FPGAs" are increasingly useful to designers who need to incorporate many functions into a single chip, but the increase in size and the effects of interconnect delay put timing goals at risk. Traditional synthesis and place-and-route methods can take many iterations to achieve timing for deep-submicron PLDs containing more than a million gates as well as other resources such as memory and an embedded processor. Maintaining the core value of programmable logicfast turnaroundrequires a design methodology that can meet aggressive timing goals by actually using physical design information during the synthesis process. Physical synthesis offers the necessary solution.

Primary concern

Physical synthesis deals with the primary cause of the PLD timing problems. For bigger devices, signal delays depend more on the physical distance between logic elements and type of routing resources used to make the connection. The delay associated with interconnect dominates overall timing in today's programmable devices. If a design's critical path takes a circuitous route across a large FPGA, for example, that path is likely to meet only pedestrian timing goals. Tuning timing constraints and back annotating delay after the fact may help to a certain degree, but usually only after many iterations.

In any case, physical synthesis factors a design's physical characteristics into the synthesis process. During synthesis, a design is optimized and implemented based upon not only traditional timing constraints, but also physical constraints. The nature of FPGA architectures makes it possible to perform physical optimization techniques during synthesis, for example, moving/placing registers across regional boundaries to increase performance.

In addition, physical synthesis offers significant productivity as well as performance advantages to FPGA designers. By using physical constraints during synthesis, designs result in more accurate timing estimation, which eliminates time-consuming design iterations typically required with gate-level synthesis.

Another key issue for the design of high-density FPGAs is team design. At the multi-million-gate level, a team of engineers may be required to complete a project. Complete autonomy between team members to independently design, assign timing constraints and synthesize their portion of the design creates a timing challenge for complex FPGAs. Designers must be able to work in parallel on different portions of a design without having to guess in advance where the critical paths will be.

This requires design tools that can control the physical hierarchy. Using physical synthesis, designers can create a new physical hierarchy when a timing problem is found saving weeks of iterations and enabling the team to meet its engineering schedule.

It is also unrealistic to assume that design teams will create these large multi-million gate designs from scratchthey must use IP. The complexity of the IP available today for use with programmable logicfrom embedded processors to DSP functionalitycan enable designers to develop complete integrated programmable platforms (IPP). The benefits of these solutions are enormous.

And with 15 million-gate FPGAs slated for launch this year, the use of IP is not just a convenience for some high-end design projects, it will be a requirement for all mega-FPGAs within the next five years. And, as designers move toward integrating these disparate pieces of IP across their multi-person design teams, they will need to move to a physical synthesis approach in order to realize the true promise and benefits of their IP.

? Jimmy Chen

Director, Asia Business Development

Synplicity Inc.





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