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LSI Logic tries startup's wafer polishing approach

Posted: 06 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:lsi logic? acm research? cmp? chemical-mechanical polishing? dielectric material?

LSI Logic Corp. is exploring a new method of polishing copper and low-k interconnects by working with ACM Research Inc., which has developed a form of non-contact polishing aimed at replacing conventional chemical-mechanical polishing (CMP).

As new and softer dielectric materials with lower k-values are introduced, it becomes more difficult to protect the dielectric material from stresses incurred during the CMP steps, said Ronnie Vasishita, a technology planning manager at LSI Logic.

"We believe the 90nm node represents a point of inflection, where the very porous low-k materials will prove to be too malleable for the abrasive contact that happens during conventional CMP steps," Vasishita said.

LSI Logic and ACM Research have signed a codevelopment agreement that involves the installation of an ACM electro-polishing systems at LSI Logic's process development center in Gresham, Oregon, on April 15. The ACM approach arranges a cathode and anode over a wafer to accomplish locally controlled electro-polishing, in which small sectors of a wafer are polished in what is essentially an etching process.

David Wang, ACM's founder, said LSI Logic experimented with the ACM approach by taking a single lot of wafers and comparing conventional CMP with the ACM tool, called the Ultra-SFP (stress free polishing). Using a dielectric material with a k-value of 2.2, conventional CMP "broke the copper lines and caused delamination in the low-k," Wang said.

ACM Research also claims that its system is much cheaper to operate. The cost of materials in CMP is rising as the pads and slurries become increasingly costly, Wang said.

Vasishita said LSI Logic is likely to cooperate with Taiwan Semiconductor Manufacturing Co. Ltd on a joint process at the 90nm node. The two companies are currently codeveloping a process for the 130nm node that will be used at TSMC's fab; LSI Logic uses a slightly different process flow at its fabrication facility in Gresham. For the 90nm node, LSI Logic expects to "stick as close to TSMC's standard process as possible," Vasishita said.

That may give ACM Research an opportunity to prove itself at LSI Logic's Gresham development center, smoothing its entry at TSMC, IBM and other large customers that expect to begin production of early 90nm devices late next year, Wang said.

? David Lammers

EE Times

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