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Sonics releases memory scheduler core

Posted: 06 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:sonics? ip core? intellectual property core? memory controller? dram controller?

Sonics Inc. introduced a memory scheduler core at the Design Automation and Test in Europe conference. The IP core will sit between any memory controller based on the Open Core Protocol and the company's SiliconBackplane MicroNetwork IP, a glue for IP cores.

The Open Core Protocol (OCP) is a defined interface between IP cores and on-chip communication subsystems that is promoted by Sonics and other IP vendors.

The MemMax scheduler core provides the initiator and task information necessary to schedule memory transactions in a way that maximizes memory performance, Sonics said. The patent-pending core has demonstrated DRAM access efficiency improvements up to 40 percent greater than traditional fixed-bus approaches, according to Drew Wingard, CTO at Sonics.

"MemMax consolidates the intelligence required to effectively manage data at what is almost always the most congested target on the chipthe shared memory subsystem," he said. An optimized memory subsystem solution would consist of a MemMax scheduler, a conventional DRAM controller with an OCP interface, and DRAM chips, according to Wingard.

MemMax is configurable through a GUI and can support up to eight request threads with three level of services. The core is available immediately; predesign licensing fees start at $75,000.

Nicolas Mokhoff

EE Times

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