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CoWare adds bus synthesis to N2C system

Posted: 07 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:coware? soc design? bus synthesis? interface synthesis? n2c?

CoWare has enhanced its N2C design system with what it calls second-generation Interface Synthesis capabilities, which enable automatic synthesis of the bus interconnect matrixes and crossbar switches at the heart of multilayer buses in current SoC designs. Arbitration logic for multiple bus masters, and all other bus logic, is also synthesized by the system.

CoWare said its N2C allows designers to build accurate simulation models for different bus configurations. A designer specifies graphically which bus masters connect to which bus slaves via which node, with each node producing a distinct bus or bus layer. With second-generation Interface Synthesis, N2C removes the guesswork in making such tradeoffs.

CoWare said its technology allows a designer to mix and match master and slaves of different types and, with the Interface Synthesis technology, synthesize an implementation-specific bus topology based on the proper bus architectures, including decoders, arbiters, and bridges.

This capability has been proven in production designs using ARM's Amba 2.0 bus and STMicroelectronics' STbus, according to Pete Hardee, director of product marketing at CoWare.

"Many of our new SoC designs use the advanced features available in Amba and STbus," said Jean-Marc Chateau, director of Design, Consumer and Microcontroller Groups for STMicroelectronics. "We worked with CoWare to enhance N2C for building platform variants exploiting these advanced features."

Following simulation, N2C's analysis tools let designers check the performance of different configurations. To change from one bus configuration to another, the designer adjusts the high-level input and re-synthesizes.

Once the optimal bus architecture is established, the hardware design can be validated and implemented in an RTL-based design flow, the company said.

CoWare provides ways for a designer to mix and match different types of blocks. A typical system contains a number of connected hardware blocks, some masters (CPU and DMA, for example) and some slaves (timers and UARTs, for example). These blocks are connected via channels which may be incompatible, with different data types, primitive protocols, or bus protocols.

Most SoCs include a high-performance, high-bandwidth bus for components such as cores and memory controllers, and another bus for lower data-rate peripherals such as serial or parallel ports, UARTs, and timers. The logic used for communicating between the bus structures needs to be configurable, based on the data rate and the number of masters and slaves.

In addition to standard buses such as Amba, STbus, and IBM's CoreConnect, many companies use proprietary buses. Bridges are required not only to join buses of the same type but also to bridge between different bus standards. CoWare's Interface Synthesis enables the synthesis between these different bus structures, the company said.

Nicolas Mokhoff

EE Times





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