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SoC stumbling blocks cataloged at DATE

Posted: 11 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:design automation and test in europe? virtual silicon technology? soc? electronic design automation tool?

It's not enough to be fast, efficient and technically proficient. Designers now must become Renaissance engineers. That was the overarching message that emerged here at the Design Automation and Test in Europe conference last week. As keynote speaker Taylor Scanlon, CEO of library developer Virtual Silicon Technology Inc., put it, "Take responsibility to become a citizen of the world."

Taylor believes the success of a SoC design "is limited by the weakest IP block from a third-party vendor." Such weakness might stem from a lack of knowledge or a lack of communication among the various interested parties of a design?OEMs, IP providers, foundries and suppliers of electronic design automation tools?as the industry places 0.135m devices into production.

Echoing Scanlon's remarks, speaker after speaker at DATE's packed panel sessions came up with a list of SoC stumbling blocks: a low-power crisis, a myriad of architectures, the platform conundrum and reconfiguration issues.

"We need to build the top of the application domain pyramids, paying attention to the kind of people we need and the methodologies they need to garner," said keynoter Hugo de Man, a senior research fellow at IMEC, a research consortium in Leuven, Belgium. "Only then can we blame the tools for not doing the job."

De Man's speech called for "a new Mead-Conway methodology in the nanoscale age," referring to the VLSI design methodology that is seen as having enabled IC designs in the 1980s. "We need to reconcile IP blocks with architectures to close the [SoC] architectural gap that is based on people and methods."

In De Man's view, designers need to explore the myriad of architectures that can be assigned to the very different application domains, and then work down the "pyramid" to discover the common ground at the IP-block level. By thinking at a higher level of abstraction, he said, designers can build in early the attributes for the application they are trying to serve.

Power crisis

More specifically, the consensus at DATE was that designers are going to have to find more imaginative ways to deal with power consumption. Otherwise, they could well see dramatic rises in standby current as processes move to 100nm (0.15m).

At a power crisis panel, Mike Kliment, co-founder and chief technology officer of Virtual Silicon, said sub-threshold leakage currents are on the rise. A 20 million-transistor device in standby could draw 80mW just through sub-threshold leakage at 100nm, he said. The International Roadmap for Semiconductors says a portable device of that complexity should consume just 2.1mW.

Panelists and other experts at the conference said system-level design techniques would provide the best opportunities for saving power. But increased use of multithreshold logic cells, multiple supply voltages and active power control over blocks will be needed to deal with sub-130nm leakage problems. Higher thresholds on transistors that can run more slowly can cut the sub-threshold leakage. But tool support for the techniques is only partly in place.

Deep-submicron design "means significant changes at all levels in the design flow," said Ulf Schlichtmann, senior director for cells and memories at Infineon Technologies. The alternative is going back to full-custom design techniques.

"The heavy lifting must be done by the EDA suppliers. Along with timing and area, leakage needs to be an optimization constraint," Schlichtmann said.

David Overhauser, founder and vice president of Simplex Solutions Inc., added: "Two-thirds of the metal may be spent on power routing in an SoC. [Using] multivoltage supplies means even more of the metal being used for power routing."

Other techniques, such as reverse-biasing the body to cut leakage, can lead to increased gate-oxide logic, said Kliment. "This new leakage phenomenon is a function of voltage stress," he said.

Larger potential

For active power, "tweaking transistors doesn't gain very much," said Antun Domic, senior vice president of nanometer analysis and test at Synopsys Inc. He added that techniques such as re-encoding state machines can get power savings of 40 to 50 percent. "But the largest potential is at the system level," said Domic.

System-level solutions aimed at relieving the power crisis were offered at the "network on a chip" panel, where presenters from Agere Systems Inc. and Philips Research Labs detailed their work on using the principles of communications systems in SoC design. "We postulate that SoC interconnect design can be done using a micronetwork, which is an adaptation of the [communications] protocol stack," said Giovanni De Micheli, professor at Stanford University's Computer Sciences Labs.

Joseph Williams, principal research engineer at Agere, detailed an ongoing project first proposed at the International Solid-State Circuits Conference two years ago: "Agere's Daytona programmable DSP platform is an example of applying many of the techniques developed for data networks to SoC design," he said.

In developing its Aetherreal Network-on-Silicon (NoS), Philips decided to use a combination of circuit and packing switching, a la asynchronous transfer mode, to enable communications between IP blocks. Philips managers described NoS as "a hardware architecture with a programming model based on the OSI reference model, which allows the structuring of communication complexity from the physical implementation up to the application in a number of layers." In this way a communications-centric architecture in an SoC can be used to serve numerous specific applications, possibly leading one day to an entire application-specific SoC industry.

This trend was endorsed at the conference's CTO panel by Wally Rhines, chairman of Mentor Graphics Corp. "The move toward platform-based design is going to enable specialized vertical end markets with design platforms dedicated to them," he said.

Interface opportunity

Certainly, new approaches and new ways of thinking about designing SoC devices need to be nourished if the industry is to take advantage of the next commercial opportunities, said Cadence Design Systems CTO Ted Vucurevich. "If the '70s gave us ICs, the '80s computing, and the '90s the communications and information infrastructure, then the next opportunity for the industry is interface devices." Vucurevich echoed de Man's point in his keynote speech that microelectronics will converge with nanotechnology by 2010.

De Man endorsed the concept of "R&E," research and education, as a means to get there from here. "The holy trinity of the past of university research, government backing and industry results needs to be resurrected as specific centers of learning, research and development," said de Man. "In such an environment the educated professional will be able to contribute much faster to final products by understanding the end goals and working toward them in a disciplined environment."

He pointed to the Gigascale Silicon Research Center and the Berkeley Wireless Research Center as two such venues.

? Nicolas Mokhoff and Chris Edwards

EE Times





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