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Synopsys, UMC develop signal-integrity test chip

Posted: 12 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:synopsys? umc? universal microelectronics corp? signal integrity tool? test chip?

Synopsys and UMC announced they have developed the ATG-SI test chip for researching signal-integrity effects on designs developed in UMC's 0.13?m Fusion process. The chip contains test structures that allow the study of multiple threshold voltages, inductance effects and model extraction.

The chip also tests other signal integrity issues, including crosstalk and noise, which affect the performance and reliability of SoC designs. The test chip addresses the requirements of digital, analog, RF and mixed-signal designers who are targeting their designs to 0.135m and below copper process technologies.

Also manufactured in UMC's 0.13?m Fusion process, the ATG-SI evaluates inductive coupling of global busses routed in the thick copper top layer using both standard driver-receiver pairs and differential on-chip signaling.

The ATG-SI also contains an expanded matrix of crosstalk capacitive coupling experiments to explore the impact of the timing differential between an aggressor and a victim's switching edges on the overall timing of each path.

The 0.13?m Fusion process is claimed to allow both high-speed and low-leakage transistors to be integrated into a single IC. This allows designers to create chips that can meet the high performance demands while maintaining low power flexibility.

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