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Vendors join push for assertion standards

Posted: 13 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:international hdl conference? ic verification?

The strongest effort yet to forge a standard assertion language for IC verification will unfold at the International HDL Conference (HDLCon) here this week, as Co-Design Automation Inc. and Real Intent Corp. announce the donation of the Superlog Design Assertion Subset (DAS) to the Accellera standards organization. With open backing from seven other verification providers, the donation could avert a looming "language war" among proprietary assertion formats.

The new effort, however, doesn't yet have backing from any of the four major EDA vendors?Cadence, Synopsys, Mentor Graphics or Avanti. And Accellera now has three separate initiatives aimed at assertion or formal property languages, opening the door to possible confusion.

Assertions are viewed as a critical verification tool because they allow properties?for example, "a request must always be followed by an acknowledgment in two cycles"?to be tested directly in either formal verification or simulation. But with a number of new and existing vendors offering their own assertion language formats and languages, the EDA industry was heading for serious interoperability problems.

"Lots of different companies are producing their own assertion formats for their own tools, and users have to rewrite assertions over and over again," said Dave Kelf, vice president of marketing at Co-Design Automation. "What's required is a set of assertions that can be applied across a range of tools."

The Co-Design/Real Intent Superlog DAS is the "best-thought-through solution to the assertion problem," said Gary Smith, chief EDA analyst at Gartner Dataquest. "There's a long way to go to solve the assertion language standard problem, but this is a promising start."

The Superlog DAS was created by both Co-Design, which contributed its simulation expertise, and Real Intent, which helped make the assertions usable in formal model checking. The DAS will work with any Verilog verification tool and does not require the use of Co-Design's Superlog language, Kelf said.

But there are skeptics, including Averant Inc., which continues to push its own assertion language. "The feedback on our language has been universally the same: It is easy to learn, it is elegant and it is a language designers can use," said Averant president Ramin Hojati. "We hope to have it eventually become the standard language. Today, it is the most widely used commercial language."

Vendors endorsing the Co-Design/Real Intent initiative include Verplex Systems, Novas Software, 0-In Design Automation, Axis Systems, Tharas Systems, Veritable Inc. and Synapticad. Buy-in from the four largest EDA vendors will be important, since they collectively hold the lion's share of the verification market. Co-Design and Real Intent would not confirm any contact with those companies before today's announcement.

Accellera thrusts

The Superlog DAS will be donated to the Accellera standards organization's HDL+ (also called System Verilog) committee, which is working on extensions to the IEEE 1364 Verilog standard. Two related but separate Accellera efforts include the Verplex Open Verilog Library (OVL), and the attempt by the Verilog Formal Verification (VFV) committee to standardize a formal property language.

The efforts are complementary, said Harry Foster, chief technology officer of Verplex and chairman of the VFV committee. "The Co-Design donation is a proposal for an extension to the IEEE 1364 standard by adding a nice assertion mechanism directly into the Verilog language," he said. "Keep in mind that this assertion mechanism would not work in VHDL."

The VFV committee, in contrast, is not looking at Verilog extensions but seeks to standardize a new, formal property language. It originally considered four candidates: ForSpec, from Intel; CBV, from Motorola; Sugar, from IBM; and "e," from Verisity.

Intel made a concerted push for ForSpec in the fall, but the VFV committee has since eliminated it as a standards candidate, said Greg Spirakis, director of design technology for Intel's architecture group. "We had hoped the committee would use it [ForSpec] as a starting point, but they've chosen not to," he said. "We're continuing to work with Synopsys, Verisity, Co-Design and others to get out a new revision of the spec within the next few months."

"Formal property languages are much more powerful and complex than a simpler, RTL assertion mechanism," said VFV's Foster. "It's like operating a Boeing 777 compared with a Volkswagen. In the short term, I don't see RTL designers using formal property languages. They'll be adopted sooner by design architects and verification engineers."

Foster said the DAS is also complimentary with Open Verilog Library and noted that he will help present a paper on that very topic at HDLCon. OVL works today in all IEEE-1364 Verilog simulators, with a VHDL version just released. The DAS, if accepted, will work in tomorrow's Verilog tools, Foster said.

"OVL is a set of basic primitives used to quickly create specific assertions, whereas this [DAS] is a language that can do much more complex things," Kelf said.

"The problem is that Accellera has a lot on its plate right now. I think the community is quite confused about all these activities," said Richard Curtin, chief operating officer of verification startup @HDL Inc. Curtin said that his company will support whatever standard develops but that @HDL is not on the current list of Superlog DAS supporters.

Cooperative effort

Development of the Superlog DAS was a cooperative effort between Co-Design and Real Intent, with contributions from Novas, 0-In and Verplex, according to Kelf. A key motivation for the cooperation was the development of an assertion subset for both simulation and formal verification.

Kelf said that Co-Design's Systemsim simulator previously had an assertion mechanism but that it was aimed only at simulation. Real Intent's knowledge of formal verification, derived from its Verix product line, allowed an assertion subset that works for both simulation and formal verification, he said.

"Formal analysis typically has a zero-delay view of the design," said Prakash Narain, Real Intent's president and chief executive officer. "The original [Systemsim] assertions were asynchronous. We suggested modifications that will retain the checking capabilities needed for simulation, while adding a synchronous view of the assertions so they can be applied to formal model checking."

While seven other EDA vendors are backing the Co-Design/Real Intent effort, thus far only Verplex Systems Inc. has licensed the Superlog DAS. Dino Caporossi, vice president of marketing at Verplex, noted that his company donated a requirements document that was used as a basis for the assertions and that it reviewed the resulting subset.

"The extension proposed is a relatively straightforward and natural extension of Verilog that should gain wide support," said Prab Varma, president of verification startup Veritable. He noted that the lack of an "assert" capability in Verilog has led many companies to reinvent their own assert directives or assertion libraries.

While Veritable plans to support the Superlog DAS with its Verity-Check property checking tool by the third quarter, the company will continue to support and enhance its own Verity-Check property specification language, Varma said.

Similarly, 0-In Design Automation will continue to support its existing CheckerWare library and "pseudo-comment" assertion mechanism, while also endorsing the Superlog DAS. "The donated [DAS] construct provides an efficient mechanism for specifying basic assertions based on equations and temporal properties," said Tom Anderson, vice president of applications engineering at 0-In. "The checkers in our library map directly to higher-level design structures such as state machines, arbiters, FIFOs and memories."

Synapticad Inc. will add the ability to generate Superlog assertions to its TestBencher Pro product by the fourth quarter, said Donna Mitchell, Synapticad's vice president of marketing. "Basically we are adding the ability to generate temporal assertions directly from graphical timing diagrams," she said.

Novas Software Inc. is "not licensing the DAS at this time," said Scott Sandler, president and chief executive officer. But "we have worked with Co-Design to help refine the language, and we believe that it provides a quality starting point for standardization," Sandler said.

Representatives of both Axis Systems Inc. and Tharas Systems said they intend to support whatever Accellera assertion standard emerges with their respective hardware-assisted verification tools.

But Averant's Hojati thinks things are moving along a little too quickly.

"We are concerned that at this time, the industry collectively does not have sufficient real-world experience to design and freeze a standard language," Hojati said. "We are also reluctant to freely contribute what we have paid a high price to learn."

? Richard Goering

EE Times

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