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Motorola MPU performs up to 125 Dhrystone 2.1 MIPS

Posted: 14 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:motorola? embedded systems conference? microprocessor? core microprocessor? coldfire?

Designed for audio electronics, imaging, security/biometrics, and industrial control applications, the MCF5249 microprocessor features a performance of up to 125 Dhrystone 2.1 MIPS at 140 MHz, while consuming 1.3mW/MHz.

Based on the ColdFire 32-bit microprocessor architecture, the MCF5249 also boasts 96KB of on-chip SRAM, 8KB of instruction cache, two independent UARTs and 16-bit timers, and a PLL clock. It also features software watchdog timer, GPIO lines, two I?C interfaces, QSPI, 4-channel DMA, and a glueless SDRAM controller.

The device also integrates an on-chip 12-bit DAC and an enhanced multiply-accumulate (eMAC) unit to provide DSP functionality for fast math and signal processing capability for audio and other applications. The ColdFire V2-family development tools support the 160 MAPBGA device.

The MCF5249 is priced at $10.30 each in quantities of 10,000 units. A 144 LQFP version of the device is planned to be available later this year.

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