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Agere multi-terabit switch fabric targets metro and core networks

Posted: 14 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:agere? embedded systems conference? network chipset? networking chipset? switch fabric?

Agere Systems has announced at the Embedded Systems Conference in San Francisco, the availability of its PI-40 protocol-independent multistage, multi-terabit switch fabric for high-performance metro and core infrastructure networks.

Offering the industry's first provisionable OC-12c to OC-768c interfaces, the solution combines switching with serdes technology to perform terabit routing at the core of the Internet, and aggregation at the edge of the network. The solution can also be used in service-aware switches and provisioning platforms, broadband access equipment, and SANs.

Based on the company's Atlanta chip memory space memory switching architecture, the PI-40 solution helps speed time-to-market as well as lower system cost, space and power for network OEMs, and is also claimed to simplify complex router and switching system design, while increasing line speed and system capacity.

The switch fabric consist of the PI-40X for aggregation/concentration, queuing and scheduling, the PI-40C for crossbar arbitration and switching, and the PI-40SAX, a single-chip standalone 40Gbps switch that includes the capabilities of the PI-40X and PI-40C.

The PI-40X and PI-40C are QoS-preserving fabrics that linearly scale in chip count from 80Gbps to 2.5Tbps. They support up to 1,024 ports and are non-blocking in construction. The PI-40X uses advanced queuing structure to avoid HOL blocking, and can switch full-duplex 40Gbps user data. It also integrates 40 2.5Gbps full-duplex integrated serdes I/O ports with integrated CDR.

The PI-40C performs arbitration and crossbar functionality at 160-by-160Gbps. It integrates 64 2.5Gbps full-duplex integrated serdes I/O ports with integrated CDR.

Both devices consume 1W/Gbps of switching traffic and extends support to ATM, IP, and TDM traffic by supporting a programmable selection of cell payload sizes of 64 bytes, 72 bytes and 80 bytes as well as advance scheduling.

The PI-40 offers high QoS and features end-to-end flow control, as well as advanced traffic management features for VoIP, SLAs, and VPNs. The solution also supports both 1+1 and 1:N fabric redundancy as well as both unicast and multicast switching with separate embedded cell buffers for each kind of trafficwithout the need for external memory.

The PI-40 scheduler supports three scheduling policies to ensure QoS: strict priority for high priority traffic, guaranteed bandwidth for real-time traffic, and weighted round robin for best effort traffic. These scheduling policies, combined with support for three levels of back pressure?device level, port level and queue level?provide system designers absolute control over traffic flow.

The solution comes bundled with a Java-based performance simulator tool that can operate on Unix Solaris, Windows NT/98/2000. The simulator replicates the performance of the devices and includes a traffic generator/analyzer that can generate input data streams to the fabric, interpreting simulation results in a meaningful format.

It also provides statistical performance parameters of the fabric, including average latency, maximum and minimum latency, and maximum fabric port data. The simulator also supports multiple I/O configurations to evaluate product capability for specific application requirements.

The PI-40X is packaged in a 1,788 FCBGA and is priced at $1,100 each in 1,000-unit quantities. The PI-40C is packaged in a 1,325 FCBGA and is quoted at $1,230 each in 1,000-unit quantities.





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