Views of IC quality are clearly different at ISQED

The opening plenary session of the International Symposium on Quality Electronic Design inadvertently reenacted the proverb of the blind men and the elephant, Tuesday (March 19).

Executives from very different parts of the electronics industry?all of them seeing quite clearly?described the problem of design quality in profoundly different terms. The result was a series of significant insights into the quality issue, and an implicit revelation about the need for interdisciplinary communication.

Leading off the session, Synopsys Inc. senior vice president and general manager John Chilton examined quality from the viewpoint of a seasoned intellectual-property provider and consumer. Chilton's working title was "IP: Intellectual Property or Intense Pain?"

Chilton suggested that the electronic design automation industry's notion of design reuse simply didn't occur in practice. Instead of creating reusable blocks that go into a repository, he argued, designers in real life are under too much pressure, and create single-use blocks.

What can work, Chilton claimed, was either of two approaches. In one approach, a commercial IP company intentionally creates reusable blocks and supports them for customers. In the other model, designers implement blocks as needed, and then put them in an archive Chilton called a scrap heap. Then a dedicated reuse team takes valuable-looking blocks out of the scrap heap and redesigns them to comply with reuse standards, finally entering them in a repository.

Paradoxically, the most valuable parts of these blocks are the verification bench, the documentation and then the RTL [register-transfer-level] code, Chilton said. What was vital to the reusability of IP, he continued, was quality. The executive said Synopsys learned that keeping the design and the specification congruent throughout the process; close adherence to design rules and defined practices; and remaining within the envelope of the available tools were all vital components of quality design.

Coming from an entirely different viewpoint, Y. David Lepejian, president, CEO and chairman of HPL Technologies described the chain of events by which inadvertent choices in the design process create critical structures on the die, leading to depressed yield. "In a world where products have a two- or three-year life, we can't wait 24 months for a manufacturing team to find the critical areas on the die and improve yields," Lepejian said. "We have to understand the critical factors for a given process at the beginning, and design in such a way as to minimize their density." For Lepejian, whose company creates IP for test chips, this process starts with a test chip fabrication. Patterns on the chip are used to indicate what structures on actual designs will be the most failure-prone. Then the physical design of the chip is arranged to minimize the density of these critical features, and to warn manufacturing of die areas in which critical feature density remains high.

Bringing in the foundry perspective, Jim Kupec, formerly president of UMC USA and now chief executive officer of startup AmmoCore Technology Inc., discussed what did and did not limit yield from a foundry perspective. Kupec said that dice up to 2-by-20mm have been and will remain economical with existing steppers. Their area by itself does not create low yield. Rather, he argued, it's what goes on the die that is usually the problem.

Kupec suggested that an IP vendor should be evaluated not like a parts supplier, but like a potential employee. "Don't just evaluate the core-check references," he stated. Kupec added that he meant that literally: picking up the phone and calling designers who had used the core previously in similar circumstances. For analog IP, his advice was even more stern: "Do not use a piece of analog IP on a large SoC unless you have previous, first-hand silicon experience with it," Kupec warned. "That means you've used it before or you have run a test chip."

Finally, Buno Pati, president and CEO of Numerical Technologies Inc., related the role that his company's tools would play in ensuring quality for designs below 180 nanometers.

The loss of what-you-see-is-what-you-get immediacy in design, in Pati's view, interferes with a number of the verification steps that used to be in place for chip design. From physical design through DRC and LVS checking and mask inspection, the design has to be compared not against a design of ideal polygons, but against a simulation of what the design's patterns will create on the silicon. This in effect removes optical-proximity-correction features and phase plates from the GDS-II data and replaces the GDS-II with an image of the mask imprint on the silicon, making checking once again feasible.

Pati concluded by addressing the question of how much further optical lithography could go by showing a micrograph of a 9nm feature created with a 248nm optical column.

Taken together, all of the speakers made clear points. But they also made it clear that they were expressing nearly unrelated points of view.

Implicitly, the keynote speeches cried out for a summit conference between chip designers, IP providers, process engineers and library creators to address the problems about which each one now speaks with a different voice.

? Ron Wilson

EE Times