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Fab revamp delays Lattice Semiconductor's FPGA architecture

Posted: 27 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Lattice Semiconductor? FPGA? UMC? Agere Systems? dielectric?

Lattice Semiconductor has been forced to delay the introduction of its own-design FPGA architecture to the end of the second quarter because of streamlining at one of its foundries.

Taiwanese foundry UMC, Lattice's supplier, has ended production at one of its fabs, forcing the chip company to transfer the process and the design for the FPGA to another UMC facility. Although the second fab supports the same process, Lattice is requalifying the sub-0.18?m technique, incurring at least a three-month delay.

Lattice has launched a separate series of FPGAs produced by the design team that it acquired from Agere Systems late last year. These focus on comms-oriented applications.

Lattice plans a more generic family based on an architecture brought in as part of its acquisition of Vantis from AMD in 1998. Stan Kopec, vice-president of marketing for Lattice, says the Vantis architecture "has mutated substantially since then".

Last year, UMC said it would streamline production to focus on a smaller number of 12-inch lines in favour of 8-inch production. At the start of 2001, the company had six fabs in production on 8-inch lines, but closed its 8B and 8F sites because of low capacity utilisation.

Cyrus Tsui, Lattice's chairman and CEO, said, "The FPGA was slated for introduction at the end of last year. It is scheduled now probably for the end of Q2. Half of that delay is because of the fab shutdown. It is the same process but at a different fab."

The Agere parts are being built at another foundry, TSMC, on a 0.16?m process with aluminium wiring and transistors running from 1.5V. Tsui says continuing problems with low-k dielectrics in terms of manufacturability and reliability on copper processes mean there is very little foundry production of true 0.13?m devices.

"If you see a lot of announcements on 0.13?m but with a core voltage of 1.5V, you know it is not a true 0.13?m process. Ours is an honest 0.16?m," said Tsui.

"It is the sooner the better [for devices to move to] copper, but that will be as soon as the low-k dielectric becomes reliable."

? Chris Edwards

EE Times





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