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IBM, Sony and Toshiba to co-develop advanced chip processes

Posted: 04 Apr 2002 ?? ?Print Version ?Bookmark and Share

Keywords:IBM? Sony? Toshiba? SOI? semiconductor?

In a deal that will move silicon-on-insulator (SOI) and other advanced semiconductor process technologies into cost-sensitive consumer electronics ICs, IBM Corp., Sony Corp., Sony Computer Entertainment Inc. and Toshiba Corp. have signed a four-year process technology development agreement.

The agreement, announced here Tuesday (April 2), will focus on the 90nm, 65nm, and 45nm technology nodes, deploying copper and low-k interconnects, SOI, and eventually high-k dielectrics, strained silicon, and double-gate structures, according to IBM.

The technology agreement will complement the "Cell" computing partnership signed March 12, 2001, that focuses on computer architecture and chip design issues for the Playstation 3 console and other "post-PC" platforms. Last year, Sony separately signed a parallel agreement to have IBM share some of its 90nm process technology with Sony.

Bijan Davari, IBM vice president of technology and emerging products, said the new agreement puts IBM's most advanced process technology, called the "S" process, into a joint process technology relationship. By contrast, IBM's ongoing technology development program with Infineon Technologies and United Microelectronics Corp. involves the less-advanced "SF" technology, which does not include SOI, strained silicon, and other cutting-edge advances.

Beginning with the end user

Davari said the latest agreement will allow Sony, one of the world's largest consumers of silicon, to provide key input to both IBM and Toshiba; the latter company has mass-produced chips used in Sony's Playstation 2 game console. While IBM's initial 90nm (0.95m) technology has been largely defined and will be deployed late this year, the agreement brings together the partners at the technology definition phase of the 65nm node, expected to reach mass production by late 2004 on 300mm wafers.

"Sony will be engaged in the technology development of processes used for low-power and low-cost chips, using our highest performance process. This brings the end user together with the technology at the development stage," Davari said.

About 50 to 100 engineers from Sony and Toshiba will be relocated to East Fishkill, New York, to work with a larger group of IBM engineers and scientists at IBM's Semiconductor Research and Development Center.

Ken Kutaragi, chief executive officer of Sony Computer Entertainment, said "incorporation of these cutting-edge process technologies into various audio, visual and IT products, as well as to the computer entertainment system, is expected to bring even higher competitive power to the entire Sony Group."

Significantly, the agreement will spread IBM's process advances to Toshiba, now considered the world's second-largest chip producer after Intel Corp.

Takeshi Nakagawa, in charge of Toshiba's semiconductor operations, said, "Technologies like SOI are essential for high-end and low-power SoCs [system-on-chip designs]. We expect collaboration on SOI process technology to advance joint-development of the next-generation broadband processor, and to provide a strong underpinning to our development of leading-edge products. We will apply SOI process technology to broadband processor-based LSI for such applications as a high-speed home gateway and future low-power mobile products."

Major push for SOI

IBM has used SOI in its microprocessors, but thus far has not deployed it for high-volume consumer products that must meet stringent cost objectives. While Sony has to some extent subsidized the cost of the Playstation 2 game machines in order to reap profits from the software, that strategy is limited to the game market. In order to penetrate the wider mobile computing market, the cost of the SOI wafers must be reduced. Now, an SOI wafer costs several hundred dollars, compared with less than $100 for a bulk silicon wafer at the 200mm diameter.

But IBM argues that as the industry continues to scale down the size of IC transistors and operating voltage, SOI will be needed for markets that require both high performance and very low power consumption. Costs will come down as volumes increase and the wafer infrastructure develops to produce less-costly SOI substrates, Davari said.

"We have been saying all along that not only will SOI be used for mass-market devices, it must be used. Because of the power density issues ahead of us, any leading-edge semiconductor manufacturer will have to use SOI. As integration proceeds, there is very little chance that companies will be able to keep power density on a flat line," the IBM technologist said.

The higher transistor counts and higher frequencies made possible with advanced process technologies can be partially offset by reduced operating voltage, Davari said. But as operating voltage goes to 1 volt and below, the need for SOI rises, he said.

"Some companies today use all kinds of tricks to keep power density within reason. Perhaps they say the mobile processor is a 1GHz processor, but then they reduce the frequency during certain operations, turn off half the circuits, and use other tricks. That doesn't work when you are running a speech-recognition interface on a battery-operated device that is meant to be turned on for weeks at a time," Davari said.

Toshiba brings a wealth of process technology expertise to the partnership, Davari emphasized. The company is "extremely strong" in lithography, mask making and other areas, he said.

IBM has built a 300mm wafer fab at East Fishkill that is scheduled to move into manufacturing this quarter, starting with 130nm designs. By late this year, a 300mm self-contained development fab will be opened to bring up the 90nm and finer process technologies co-developed by the four partners.

? David Lammers

EE Times

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