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CoWare links system-level tool to Xilinx flow

Posted: 10 Apr 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? CoWare? N2C system-level design tool? Virtex-II? programmable chip?

Xilinx Inc. and CoWare Inc. are tailoring Co-Ware's N2C system-level design tool to create a design flow for Xilinx's newly announced Virtex-II systems-on-programmable-chips.

The collaboration is Xilinx's latest move to expand FPGA use beyond its traditional customer base of hardware designers to embedded software and system designers. Xilinx has developed its own co-design flow for embedded designers but is teaming with CoWare and other commercial tool vendors, like Cadence, Synopsys, Synplicity and Celoxica, to attract a wider audience.

The CoWare/Xilinx flow will let users program the hardware and software of the new Virtex-II Pro FPGAs, which contain an embedded PowerPC 405 processor, as well as the rest of the Xilinx Virtex-II series FPGAs, which use the soft MicroBlaze processor core.

"This announcement should be a wake-up call that C-based and system-level design is going mainstream," said CoWare chief executive officer Alan Naumann. "With SoPCs, this is the first time that system- and C-based design is attaching itself to a mainstream design flow. The design challenge has moved from just hardware to embedded software and firmware.

"Xilinx users are going to have a need to design and architect around hardware and software in a much different way, and they are going to need a tool like N2C to make it happen."

The companies thus far have connected the N2C flow with Xilinx's recently announced System Generator, which is said to let embedded engineers automatically generate hardware and software components with the push of a button. The companies plan to demonstrate the new flow next week at Programmable World 2002 and to have the completed package ready by midyear.

The solution is not yet complete: The companies are creating models of the PowerPC core, its bus and peripherals so designers can use N2C with Xilinx's suite for Virtex-II devices more effectively.

CoWare's chairman, Guido Arnout, said the N2C system will sit on top of System Generator.

With N2C, system architects can explore architectures, make system-level design trade-offs and do "what-if" analyses to determine how best to partition the hardware and software for a design. Arnout said that software and firmware developers can then use the high-level system model to further develop the software while hardware engineers refine the high-level dedicated hardware blocks to RTL for logic synthesis. Full, at-speed final verification can subsequently be performed by running the software on the hardware-programmed FPGA.

Simpler implementations

For simpler implementations, Arnout said, once users decide on a partition with N2C, that information can be sent to Xilinx's System Generator, which will automatically generate hardware blocks as well as software blocks.

"N2C gives users the ability to explore different alternatives at a high level of abstraction," said Ivo Bolsens, Xilinx's chief technology officer. "The tool will add value in the high-level optimization steps, while System Generator will help with the implementation of the system-level design the designers and architects created with N2C."

Bolsens said tools like Co-Ware's are "essential technology" for further proliferating the usage of SoPC. "We have to spend a lot of effort coming up with a total solution that in the end gives the system designer the capabilities for exploiting all the features becoming available on our new devices," he said. "N2C will help them do this."

Since the launch of the Virtex-II Pro devices last month, Bolsens said, embedded-software designers anxious to obtain the new devices have contacted Xilinx. Thus far, however, the silicon is only being produced in engineering-sample quantities.

"With the capabilities we have now, we have been getting and expect to get more interest from a whole new group of people," said Bolsens. "The challenge will be to make sure we understand their requirements and methodologies and give them tools that will handle their needs?give them a tool that has a software look and feel but is targeted for FPGAs."

? Michael Santarini

EE Times

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