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TransEDA SoC verification tool combines emulation, simulation results

Posted: 11 Apr 2002 ?? ?Print Version ?Bookmark and Share

Keywords:vn cover emulator? verification navigator? quickturn cobalt plus? vstation? xcite?

Designed to accelerate SoC verification, TransEDA plc's VN-Cover Emulator allows users to collect coverage data, and merge them with simulation results to measure a design's verification completenessidentifying areas in the design that have been emulated or under-emulated.

The emulator provides statement coverage for the identification of dead codes, branch coverage for the identification of control logic errors, and toggle coverage to highlight problems with signal controllability.

"Our customers have demanded a unified coverage environment between simulation and emulation," said Tom Borgstrom, vice president of marketing, TransEDA. "Because every minute of emulation time is critical, customers are constantly looking for ways to complete emulation sooner."

"VN-Cover Emulator is a powerful productivity aid, providing objective, quantitative feedback that enables the emulator user to stop emulating sooner with more confidence of first-pass silicon success," he added.

"With the availability of the TransEDA coverage tool in this environment, we expect to see a significant reduction in ASIC design verification times with fewer design escapes found in silicon," said Anthony Gold, VP of engineering at Unisys.

The solution is available with emulation modes including full support mode for accelerated co-simulation, synthesizable test bench, ICE-tracer, vector regression, and in-circuit emulation.

A part of the company's Verification Navigator verification environment, the VN-Cover emulator extends coverage support for Cadence Design Systems' Quickturn CoBALT and CoBALT Plus, IKOS' VStation Emulator, and Xcite and Xtreme verification systems from Axis Systems.

The VN-Cover Emulator is priced at $50,000 for an annual subscription license.





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