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ISSI deploys SigmaRAMs on 0.135m CMOS process

Posted: 10 Apr 2002 ?? ?Print Version ?Bookmark and Share

Keywords:sigma 1x1dp? sigma 1x1lp? sigma 1x1lf? sigmaram? sram?

Claimed to be the first SigmaRAM devices to be manufactured using 0.135m CMOS with copper process, Integrated Silicon Solution Inc.'s SigmaRAM SRAMs consume 500mA during operation and are available in three different R/W protocol.

The Sigma 1x1Dp device has a double late write and pipelined read/no bus turnaround protocol, and suited for high-end switches, routers, and aggregators due to its fully random access capability to any address to perform R/W without bus latency.

The Sigma 1x1Lp device is designed as an external cache solution for embedded processors that require high density and bandwidth buffering with a Late Write and Pipelined protocol. The Sigma 1x1Lf version is designed for high-performance test equipment where buffering with a flow-through read operation is generally preferred.

The SigmaRAM devices offer 1.8V power supply, and 1.8V and 1.5V I/O LVCMOS interface, with maximum standby currents <100mA and 75mA, respectively.

Available in by-36 and by-72 configurations, the 18Mb devices are shipped in a 209-ball BGA package measuring 14-by-22m with a 1mm ball pitch. It is available with clock speeds of 200MHz, 225MHz, and 250MHz.

Pricing for the 250MHz SigmaRAM SRAMs starts at $100.





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