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NurLogic PHY core provides 12.8Gbps bandwidth

Posted: 12 Apr 2002 ?? ?Print Version ?Bookmark and Share

Keywords:amberbridge? phy core? hypertransport? ic design? embedded system design?

Manufactured using a 0.135m CMOS process, the AmberBridge HyperTransport PHY core from NurLogic Design Inc. provides an aggregate bandwidth of 12.8Gbps and has been developed for designers of high performance networking, telecommunications, and embedded systems, as well as consumer electronics and Internet devices.

This PHY core consists of three components: transmitter, receiver, and impedance calibrator, and relies on enhanced LVDS signaling technology. Testability features have been incorporated into the core design to give chip designers greater flexibility.

The AmberBridge core is compliant with the HyperTransport Technology PHY Interface Specification (v1.01) and the HyperTransport I/O Link Protocol Specification (v1.03). NurLogic offers the PHY core as a "hard" IP block that includes support for leading EDA tools and foundry technologies.

HyperTransport interconnect technology is a high-performance, low-latency, point-to-point link for interconnecting ICs. It complements externally visible bus standards like PCI, as well as PCI-X, InfiniBand and 10Gb Ethernet.

The technology helps reduce the number of buses while providing a high-performance link for PCs, workstations, and servers, as well as other embedded applications and highly scalable multiprocessing systems. It is designed to allow chips inside of PCs, networking and communications devices to communicate with each other up to 48 times faster than existing bus technologies.

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