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Researchers propose dual design verification model

Posted: 15 Apr 2002 ?? ?Print Version ?Bookmark and Share

Keywords:design verification? RTL? design verification methodology? Wipro? ASICs?

Indian researchers are proposing a novel verification methodology that uses two representations of a design throughout the verification process, one a behavioral model in C and the other an RTL model. The dual design verification methodology (DDVM) is intended to replace traditional methods and tools considered inadequate to handle complex, deep submicron designs.

Presented at a recent conference here by Sanjeev Patel of Wipro Technologies, the methodology was used to verify a three-piece network processing chip set that Wipro designed for a networking startup's high-end Internet Protocol edge routing switch. The chip set supports OC-192 (10Gbps) rates.

The problems of verifying and achieving timing closure for such complex designs are not well addressed by traditional verification methods, Patel said. New methods use higher levels of abstraction to speed up development time, and use static methods such as static timing analysis and formal verification for timing and functional integrity checks, he said. DDVM balances traditional approaches with newer ones, eliminates wasteful processes and implements consistency checks throughout the development cycle, he said.

"Our methodology combines a new functional verification approach with the static verification methods to achieve faster functional and timing validation," he said. Explaining DDVM's dual approach, Patel said the behavioral model in C is developed during a high-level design phase and is used as a reference to check the RTL representation. It is used not only in ASIC-level and chip set-level simulations, but also in software testing, he said.

Significant development

Early identification of key design issues was important in order to incorporate checkpoints and a strategy for future work into the DDVM, Patel said. The variety of configuration options required in network processing involves a high-speed, on-chip system bus to deal with the heavy loading and fan out of common signals. The net processors were also provided with on-chip debug features and numerous on-chip and off-chip memories, which constrained design partitioning and made timing closure harder, though these design guidelines were well established upfront.

"Verification efforts for multimillion-gate ASICs consume a significant portion of the development cycle," Patel said. "Development of reusable components and use of higher levels of abstraction for test-vector generation becomes a key challenge. Achieving high functional coverage on complex logic such as multiple instantiated microcode, programmable data inspection and formatting engines would require high-level abstraction, randomization and automation in verification."

The main challenges of the chip set's clock design, routability and timing closure were posed by skew targets as low as 150ps, the need to keep two on-chip clocks in phase, and the need to source synchronous clocking on inter-ASIC interfaces. On-chip memories occupy most of the die area and a large number of I/Os need to switch at high speed, Patel said.

But DDVM met all these challenges without compromise, he said. "This is made possible with unification of the design's reference model," Patel said. "Dual design verification reuses design abstraction, uses static methods that eliminate costly gate-level simulations and [uses] novel techniques in timing closure."

Self-checking verification

The DDVM approach provides a self-checking verification environment by using two representations of the same design, with the RTL representation validated against the C representation; the latter behavioral model is used for architectural validation of a design. Other components in the verification environment are used in all levels of verification, Patel said.

"This reuse cuts short the environment development cycle time significantly. Our approach easily paves the way for a regressionable verification setup because of the highly automated on-the-fly validation of response," he said.

Wipro Technologies now uses DDVM for many of its clients' designs, along with the company's EagleWision design flow, EagleWise verification guidelines and Wave verification environment creation tool. "Economy of integration at deep submicron geometries has taken the complexity of functional verification to astronomical heights and made timing closure a long iterative cycle," Patel said. "This methodology smartly combines novel techniques and a start-of-the-art toolset to enable defect-free silicon and thus [provides] a significant time-to-market advantage."

? K.C. Krishnadas

EE Times

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