Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Manufacturing/Packaging
?
?
Manufacturing/Packaging??

TSMC exec advocates slower steps between process nodes

Posted: 15 Apr 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Taiwan Semiconductor? TSMC? 90nm IC? IC? low-k material?

Taiwan Semiconductor Mfg. Co. Ltd said it aims to deliver its first ICs based on 90nm design rules by the third quarter of this year, about one year ahead of the time frame cited in the industry's International Technology Roadmap for Semiconductors. But the leading foundry company's chief technology officer said the chip industry needs to moderate its expectations on jumping to new process technology nodes.

Until 1995, the chip industry was on a pace to migrate to a new process technology node every three years. Since then, it has been shifting to finer process technologies every two years.

This pace may not be sustainable for much longer, said TSMC's Chenming Hu. Markets and applications need more time to digest advances in technology and production capacity, particularly now since IC sales fared so poorly last year, he said.

"One generation every three years may provide better market growth than every two years," he said. "This doesn't mean that TSMC will slow down the introduction of new technology. But I do think that there is a sweet spot for technology introduction and over the last few years we have exceeded the sweet spot."

Moving too fast

Indeed, many chip companies got burned over the last few years by investing heavily in 0.135m design rules only to watch the market nose-dive in 2001. Jordan Selburn, principal analyst with iSuppli Corp., called the 0.135m process node "the lost generation."

"There's no question that design start numbers are down substantially. By the time it picks up, 0.15m will be the design technology du jour," he said.

Aside from the economic pitfalls of moving too quickly to new technology nodes, there's evidence that technology advances are getting out of whack. The introduction of low-k inter-metal dielectric materials is one of the most glaring examples of this. While TSMC managed to reduce the k-value of the material to 2.9 when it moved from 0.185m to 0.135m design rules, the first 90nm devices will not see any initial improvement over 0.135m.

"Low-k has proved to be more difficult than expected," Hu said in an interview. "Originally the expectation was to introduce it before copper [interconnects]."

Without any immediate improvements in low-k materials, metal RC delays suffer about 15 percent performance degradation, which translates into less than 10 percent reduction in overall speed. "It's not insignificant, but it's not so large that it will stop products from being developed," Hu said.

Another drawback is that some designs will have to use looser design rules for the top metal mask layers to reduce cross-coupling and capacitance, Hu said.

To be sure, TSMC anticipates it will be able to shift to k-values of less than 2.5 for the 90nm design node. It is conducting molecular simulation on 2.1-k materials, and has a research paper that describes a way to integrate six layers of copper with 2.2-k materials.

Wavelength pressure

Lithography is another challenge. Tools with 248nm and 193nm are in use today, and the pressure is on to develop tools with narrower wavelengths. "Lithography is a more immediate concern. The important thing is to use lower-wavelength light sources," he said.

Hu said TSMC is first on the list to receive a 157nm tool from ASM Lithography Holding NV. The company is also investigating 13nm extreme-ultraviolet lithography and has developed a lithography simulation tool so it can model lithography from 65 nm to 13 nm, he said.

Another area that TSMC is pursuing is layer deposition of thin films. Using this technique, it has come up with a way to deposit a barrier film 50 angstroms thick over the surface area of via holes that are just 3.2nm-wide at the base. To boost CMOS speed, the company is looking to cap bulk silicon with layers of silicon germanium and strained silicon, which can increase electron mobility 50 percent over conventional bulk CMOS.

TSMC is also investigating silicon-on-insulator as an alternative to bulk silicon, high-k dielectrics to reduce gate leakage and double-gated finFETs that could better suppress leakage while doubling transistor current. In 2001, TSMC increased its R&D spending to about $312 million, doubling what it spent the previous year.

? Anthony Cataldo

EE Times





Article Comments - TSMC exec advocates slower steps bet...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top