Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

TSMC to offer SoC design-to-manufacturing services

Posted: 16 Apr 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Taiwan Semiconductor Manufacturing? Nexsys? SoC? EDA tool? wafer?

Taiwan Semiconductor Manufacturing Co. Ltd is moving to better coordinate the design and manufacturing flow for SoC customers with the introduction of a development architecture called Nexsys.

"It is not only a process technology, but a total solution for SoC," said marketing vice president Genda Hu. "We will have a complete design environment, from the EDA tools, which are already verified, all the way down to the place and route level. They are all in line with our process technology."

TSMC will offer the service in the third quarter for production at the 90nm node on 200mm wafers, and then on 300mm wafers in the first quarter of 2003. Hu said Nexsys will better coordinate TSMC's "family of processes" offered in logic and mixed-signal areas to provide an easier design and manufacturing interface for engineers.

TSMC announced Nexsys Thursday (April 11) at a TSMC technology forum here. During the sessions, Hu and other TSMC executives stressed the need for greater integration between design and manufacturing services as the industry follows the SoC trend. TSMC is rolling out the package to address this front-end need and also said it would increase its attention to testing and packaging services, by boosting its in-house capacity and increasing coordination with third-party sources.

TSMC also released details of an SoC process at the 90nm node. It will include a triple-gate oxide option and hit a core voltage of 1V, will support gate lengths of 45nm to 65nm and provide a best-case gate delay of 7.9ps. The high-performance process will also enable use of a low-k dielectric with a value of 2.9 and will allow up to 10 layers of dual-damascene copper metalization.

More 300mm fabs

In a related announcement, TSMC deputy chief executive officer, F.C. Tseng, said the company would break ground on two more 300mm wafer fabrication facilities in Taiwan "later this year." One will be in the Hsinchu Science Park, the other in the southern Tainan Science Park. No other details were offered. TSMC is in pilot production at Fab 12, its 300mm wafer facility in Hsinchu, and is installing the clean room at Fab 14, its second full-scale 300mm wafer fab, located in Tainan.

? Mike Clendenin

EE Times





Article Comments - TSMC to offer SoC design-to-manufact...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top