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Cadence unveils latest products for 0.13?m IC design

Posted: 24 Apr 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence? IC design? CadenceR SoC Encounter? Cadence First EncounterR?

In a bid to tackle the emerging challenges caused by increasing complexity of IC design and the advance of process technologies, Cadence Design System Inc. has introduced two new products for 0.13?m and beyond IC design. CadenceR SoC Encounter and Cadence First EncounterR Ultra integrate the Cadence SP&R (synthesis/place-and-route) solution with new advanced capabilities and technology from Silicon Perspective Corp. (SPC), which was acquired by Cadence last year.

The company said Cadence SoC Encounter is a complete front-to-back hierarchical IC implementation solution for large-scale SoC design up to 30 million gates. Cadence First Encounter Ultra provides virtual prototyping, physical synthesis, and full-chip hierarchical floorplanning and placement.

These new products combine the virtual prototyping and hierarchical partitioning capabilities of SPC's First Encounter with Cadence Physically Knowledgeable Synthesis (PKS) and Cadence CeltIC signal integrity technologies. First Encounter Ultra is designed to enable companies, such as high-end ASIC designers or customer-owned-tooling (COT) customers currently using other routing tools, to take their designs to timing qualified placement. SoC Encounter provides a complete hierarchical RTL-GDSII solution, which integrates First Encounter with the production-proven Cadence Silicon EnsembleR-PKS (SE-PKS).

? Mike Pan

Electronic Engineering Times ? Taiwan

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