NurLogic rolls out quad serdes IP cores

NurLogic Design Inc. has announced the availability of its SapphireLink serdes IP cores, which provide high-bandwidth connections between router backplane links, while supporting an 8B/10B encoding/decoding scheme with clock recovery for embedded clock applications.

The IP cores support data rates of 1Gbps to 3.318Gbps per channel and can be used in networking applications, as well as parallel-to-serial, serial-to-parallel conversions for physical and link-layer devices.

"Our technology has always played a significant role in meeting market demand for performance, low power, bandwidth, and time-to-market requirements of our SoC customers. We expect our SerDes to be well received in the industry because it places cost management, performance, and scalability in the hands of system developers," said Lisa Lipscomb, VP of marketing for NurLogic.

The 0.13?m serdes cores accept an 8/10-bit or 4/5-bit core interface with SDR or DDR options. The cores also incorporate test features including BIST, serial and parallel loopback, IDDQ, boundry scan, and Pseudo Random Bit Steam (PRBS).

The cores are implemented as 4-channel physical representations and offer a modular design that is claimed by the company to allow for multiple instantiations without performance degradation and meets the speed requirements for OC-768 applications.

They also feature a power dissipation of 80mW per Tx/Rx pair and loss of signal detection up to 90 bits. The cores also extend support for SXI5 I/Os and offer an option for eye-centered reference clock.

The SapphireLink serdes core portfolio is offered as "hard" IP blocks and is currently available for licensing.