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Virage offers multiport memory for SoC designs

Posted: 02 May 2002 ?? ?Print Version ?Bookmark and Share

Keywords:multiport memory? configurable sram? embedded system memory? soc processor memory? soc design?

Memory designer Virage Logic Corp. intends to market a configurable SRAM-based multiport memory that can perform three R/W operations simultaneously, increasing data throughput in today's embedded systems and meeting the expected demands of parallel or pipelined processors in future SoC designs.

The SRAM-based Custom-Touch Area, Speed and Power embedded memory is an extension of Virage's earlier single- and dual-port parts, but has been recast as a shared memory system for high-speed, multiprocessor SoCs.

Hoping to set it apart from competing solutions, Virage said the design will save customers silicon area over standard parts, trim design time and improve flexibility over custom-built parts. The company said it will eventually offer reliable yield data as the part moves into volume production at foundries, starting with a 0.13?m generic logic process at TSMC.

The multiported register file enables simultaneous writes to a maximum of three different addresses while data is being read from three other locations. The total number of read ports tops out at four. During the SoC design cycle, engineers may reconfigure the ports to fine-tune the optimal data throughput, Virage said.

The maximum implementation is 72Kb for one instance. For an 8Kb instance, the area and speed savings of the multiported approach versus multiple single-port register files plus logic can be up to 65 percent, the company said. The design also includes an option for DDR signaling. Pricing starts at $36,000 for one configuration.

Mike Clendenin

EE Times

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