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Aldec releases verification software for Xilinx devices

Posted: 03 May 2002 ?? ?Print Version ?Bookmark and Share

Keywords:active hdl 5.1 xe? active hdl xilinx edition? xilinx verification software? coolrunner ii? realdigital cpld?

Aldec Inc. has announced the release of the Active-HDL 5.1 XE design software designed specifically for use with high-density Xilinx FPGA devices.

The software is claimed by Aldec to support all Xilinx devices and offers a completely self-contained design entry and verification environment for Xilinx flows and tools. Xilinx libraries and TCL-based flows can also be installed directly from the software to provide a completely integrated environment for Xilinx users.

"The combination of Active-HDL 5.1XE and Xilinx ISE provides designers the tools they need to create, verify and implement their design in any of Xilinx's industry leading devices, including the new CoolRunner-II, RealDigtal Ultra Low Power CPLDs, Spartan-II FPGAs, and the Virtex-II Platform FPGAs," stated Craig Willert, Xilinx Software Product Line Marketing Manager.

The software integrates a Design Flow Manager that allows designers to control the entire design process from a single screen. They can seamlessly move from design entry through RTL simulation and logic synthesis to Xilinx implementation tools and timing simulation.

Aldec is offering the Active-HDL 5.1 XE as a keylock license, which includes Aldec's Xilinx Project Manager, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL/EDIF or Verilog/EDIF simulation.

The company has also released the Riviera 2002.03 mixed VHDL/Verilog simulator for free until the end of June. The common kernel simulation technology supports IEEE VHDL 1076-87/93 and Verilog 1364-95, including the Verilog 2001 constructs.

The Riviera 2002.03 is available for download today and supports Sun Solaris 7 and 8, Linux (kernel 2.2) and Windows NT/2000/XP.





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