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Virage pursues system-on-chip IP strategy

Posted: 13 May 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Virage? SoC? IP? embedded memory? SRAM?

Embedded-memory designer Virage Logic Corp. is pulling together a strategy for being a one-stop intellectual-property (IP) supplier to a growing number of companies developing system-on-chip (SoC) products.

In the past month, Virage has bolstered its embedded-memory line with a configurable SRAM-based multiport memory that can perform three read and write operations simultaneously, increasing data throughput in today's embedded systems and meeting the expected demands of parallel or pipelined processors in future SoC designs.

Virage also moved last week to scoop up In-Chip Systems Inc., a deal that extends its reach from memory into logic platforms for SoC designs. The price tag should fall short of $20 million, in cash and stock, for the six-year-old In-Chip and its 15 design engineers.

Through the acquisition, Virage is hoping to graft its extensive experience with embedded-memory products to In-Chip's logic savvy. Though small, In-Chip has an impressive list of customers ranging from Epson, Fujitsu and Motorola to NEC, Toshiba, Yamaha and Sony, which included some of its intellectual property in the Playstation game consoles.

"Our customers will now have the ability to source integrated SoC embedded-memory and logic platform technology from a single vendor, furthering their design reliability while increasing their production yields," said Adam Kablanian, Virage Logic's chief executive officer, in a statement.

The last few product pushes by the Fremont, California-based company have focused on the rising complexity and difficulties facing designers of highly integrated system products. To speed up a lot of these products, many types of components are gravitating toward SoC platforms. CPUs, FPGAs, ASICs and memory are among the first items being integrated on-chip.

More integration means a growing need to process more data faster, forcing designers to look at more-dynamic ways of storing and transferring information as it moves through the system. Two ways to speed this process are parallelism and pipelining, said Krishna Balachandran, director of product marketing for Virage. "In either case, the communication between the components within the chip needs to be very high speed and accessing the memory could become the bottleneck if there are not enough ports. Sequential memory accesses will not meet the cycle-time budget."

As the SoC era develops, Virage is also hoping to cash in on another potentially lucrative niche market, in which low-density, lower-cost nonvolatile memory could be the choice for products ranging from encryption keys and chip IDs to the storage of configuration parameters in Bluetooth or 802.11 RF front-end chips.

Earlier this year, Virage introduced Novea RAM, a nonvolatile embedded memory built in a generic CMOS process by implementing an approach first pitched about 10 years ago. Instead of using the more-common stacked floating-gate structure, which means extra steps for a second poly layer and an additional dielectric layer, Virage used a horizontal, folded control gate. The design isn't as silicon efficient as higher-density nonvolatile memory, such as flash, but it will do for the market Virage is targeting: EEPROMs and ROMs.

Mike Clendenin

EE Times

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