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Researchers describe embedded processor design tool

Posted: 13 May 2002 ?? ?Print Version ?Bookmark and Share

Keywords:embedded processor? Starc? HDL? ASIP?

A design tool for application-specific instruction set processors, the ASIP Meister, is claimed to increase the design productivity of embedded processors more than 100 times. The tool was jointly developed by the Semiconductor Technology Academic Research Center (Starc) and Osaka University.

"Sematech pointed out several years ago that there is a design crisis. [A] 30 percent gap exists between the growth of chip complexity and human design productivity every year. We CAD [computer-aided design] researchers have to overcome the crisis," said Masaharu Imai, a professor at the Graduate School of Engineering Science, Osaka University, who led the development project. Using the ASIP Meister, a MIPS3000-class RISC processor can be designed in about eight hours, according to Imai.

The joint research team will exhibit the tool at the university's booth at the 39th Design Automation Conference, which will be held in New Orleans, June 10 to 14. Early next month the team will start offering the tool's binary codes to academic organizations free of charge from the ASIP Meister Web site.

The ASIP Meister is a design tool for embedded processors with a pipeline architecture. From information such as pipeline operation, the ASIP Meister generates register-transfer-level HDL descriptions for synthesis and for simulations. A processor's data path and control units are generated from a behavioral description of operations per pipeline stage. Control logics such as a pipeline interlock and pipeline flush are automatically generated, which makes design and change easy. The tool supports multicycle operations, delayed branch and arbitration of resources conflict. It does not limit the number of stages.

General-purpose processors have high programmability; on the other hand, ASICs are highly cost-effective. "But it was difficult for one processor to have both advantages. Our proposal is to offer specific-purpose processors with both high programmability and high cost performance," Imai said.

Combined approaches

There are two main approaches to ASIP design: using templates or using processor description languages. Template approaches are simple but lack flexibility. Description-language approaches allow flexibility but are complex. "Making full use of [a] GUI [graphical user interface], ASIP Meister combines the advantages of both approaches," Imai said.

There are template-type design tools available on the market. But "it is difficult for these tools to set the number of stages freely and take complex instructions. ASIP Meister [has no such difficulty and] is ahead of them technically," Imai said.

The first version won't include the compiler and instruction-set-level simulator. Imai's group is now working on readying such a tool for release in one year.

The ASIP Meister will be distributed initially to academic organizations. "There has been a bottleneck [when it comes to educating] students about processor architectures. It used to take about one month for a student to design and verify one architecture, which is too time-consuming for one student to compare various architectures. ASIP Meister enables a student to test one processor in a day. We aim at fostering processor architects and system designers who have deep knowledge of processor architectures," Imai said.

Licensing considered

Outside of the academic world, Starc is considering licensing the tool to third parties to promote it. For the time being, the beta version with limited functions will be available to business users as well at the Web site.

Multimedia applications require low power consumption. Broadband communications need high performance. ASIPs can be tuned to each of those requirements. "With a good combination of FPGAs, ASIPs will have a big chance to replace general-purpose embedded processors," said Imai, who began development of the tool about 12 years ago.

Yoshiko Hara

EE Times

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