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HPL Technologies delivers yield analysis to designers

Posted: 15 May 2002 ?? ?Print Version ?Bookmark and Share

Keywords:software? HPL Technologies? IC physical design flow? electronic design automation?

In an effort to bring design-for-yield software to chip designers, HPL Technologies Inc. this week is announcing the formation of its Design for Yield division. One of the division's tasks is to forge alliances with sellers of electronic design automation tools in order to bring yield analysis and prediction software into the IC physical design flow.

Publicly-traded HPL Technologies currently sells its Yield Projector software to process engineers in semiconductor companies, including AMD, Cypress, Fujitsu, Lucent, LSI Logic, National Semiconductor and Texas Instruments. The software analyzes designs and provides statistical analysis capabilities that can help users predict, and avoid, yield problems.

"Our focus has really been on the fab side," said Mark Milligan, vice president and general manager of HPL's newly formed Design for Yield division. "But our company's vision is that every step in the product lifecycle affects yield. We need to affect yield before designs even tape out, and provide engineers with information about yield that they haven't had before."

The division will start by selling Yield Projector to design groups, and expand from there, Milligan said. "What's new is that we're providing information that makes yield actionable for the designer. It hasn't been actionable in the past," he said.

It's a worthy mission, said Gary Smith, chief EDA analyst at Gartner Dataquest. "The [HPL] technology is getting a lot of attention from users," he said. "It is a great cost savings tool now, but at 70 nanometers it could be a save-your-bacon category tool. That's where the wall between design and manufacturing falls apart."

Last month, PDF Solutions Inc. announced the launch of its Design-Based Yield Improvement service for design engineers. Smith noted that PDF and HPL are tackling the same problem, but with different business models. PDF, he said, uses a consulting model, whereas HPL focuses on selling software tools through normal licensing models.

Education mission

Education is one of HPL's primary missions, Milligan said. He compared the design-for-yield situation today to design-for-test 10 years ago, when many thought they could throw designs "over the wall" without any concern about testability. Just as chip designers today take responsibility for test, they must also learn to avoid designs that create yield problems, he said.

A second issue is moving data between design and fabrication groups, especially with the disaggregated supply chain created by the fabless semiconductor model. "We have a huge amount of data on the fab side, and the key is figuring out what's pertinent to the designer," Milligan said. "We want to leverage manufacturing data, like defect distribution models, back into design."

"A fab will have a failure rate for each silicon structure that's in a design," said Tom Jackson, director of marketing for HPL's Design for Yield division. "A via from metal [layer] 2 to metal 7 has a given failure rate. If you have a million of them, you may have problems with your yield."

HPL will also work with EDA vendors to tie its yield tools into the IC design flow. To this end, HPL has joined Synopsys Inc.'s in-Sync partnership program, said Milligan, who recently joined HPL from Synopsys. HPL is also working with Virage Logic Corp., he noted, to bring more yield predictability to embedded memories and other silicon intellectual property.

Milligan said that HPL's software-based approach offers a better solution than one based on services or consulting. "Yield decisions need to be made in the context of other design decisions, and if someone else is holding the data, it doesn't allow that to happen," he said.

? Richard Goering

EE Times

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