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Researchers seek 'green' chip-fabrication techniques

Posted: 22 May 2002 ?? ?Print Version ?Bookmark and Share

Keywords:chip? fabrication? CVD? wafer?

A research team at the University of Arizona is working to develop environmentally friendly chip-fabrication chemistries that consume fewer resources and produce fewer hazardous byproducts than conventional techniques.

"By taking the environment as a design constraint, we can build completely new chemistries that simultaneously advance technology while minimizing their environmental effects," said Anthony Muscat, an assistant professor of chemical and environmental engineering at the university, who leads at the 10-member research team. "We hope to educate a new breed of engineers who don't see polluting the environment as a trade-off."

By characterizing wafer surfaces on a molecular scale, Muscat said, environmentally benign processing steps can avoid the sources of hazardous byproducts instead of cleaning up after they are produced.

For instance, the team has already demonstrated a gas-phase cleaning technology that eliminates the need to remove, clean and reinsert partially fabricated wafers into the gas-phase reactor. Now that Muscat's team has shown that gas-phase cleaning works, chipmakers can scale the process up to mass-production levels. All of Muscat's processes are laid out in his group's publications so that any chip manufacturer can adopt them royalty-free.

A lot of engineering work remains to be done, Muscat acknowledged, before these processes can go online at major chip manufacturers. "But by demonstrating how our processes can improve both environmental impact and the cost and speed of chip processing, we hope to encourage chipmakers to make the effort to adopt our technologies," he said.

Atmospheric contaminants

Muscat's team of six doctoral candidates and four undergraduates are part of the Engineering Research Center for Environmentally Benign Semiconductor Manufacturing. Sponsored by the National Science Foundation and the Semiconductor Research Corp. and administered by the University of Arizona, its participants also include MIT, Stanford University, UC Berkeley, Arizona State University, Cornell University, University of Maryland and MIT's Lincoln Lab.

Today, chips go through several etching and chemical vapor deposition (CVD) steps during fabrication. Between many steps the wafers must be removed from the CVD reactor's vacuum chamber and cleaned with ultrapure water and other liquids. This labor-intensive step not only increases the labor-and-materials costs of chip manufacturing but can also lower yields by exposing a wafer to contaminants in the atmosphere.

By studying the molecular-level interactions necessary to clean chips during processing, Muscat's team devised a gas-phase cleaning method that allows a wafer to stay in the vacuum chamber for all its gas-phase processing steps. That avoids contamination, thereby increasing yields, and eliminates altogether the labor and expense of cleaning with ultrapure water.

Gas-phase cleaning uses supercritical carbon dioxide. "Supercritical" matter?halfway between a liquid and a gas?is produced by putting abnormally high pressure on a gas until it condenses into a supercritical fluid. The fluid lacks any surface tension when interacting with solid surfaces, so it can penetrate even the deepest etches on a wafer. Supercritical fluids also have very low viscosity, enabling them to dissolve large quantities of unwanted solids on a wafer's surface.

Muscat's team produces its supercritical carbon dioxide by subjecting it to 1,000 pounds per square inch of pressure at about 100Fahrenheit. The supercritical fluid is dense enough to dissolve both liquid and solid contaminants, yet once dissolved they easily diffuse through the carbon dioxide.

"We believe gas-phase cleaning can have an enormous environmental benefit," Muscat said. "The carbon dioxide is inexpensive, nontoxic and, after you decrease the pressure, the carbon dioxide goes back into the gas phase and the contaminating liquids and solids just drop out."

For the future, Muscat's team is characterizing the molecular interfaces between the layers of different semiconductor materials, again with an eye toward optimizing cost/speed and environmental impact. For instance, today metal nitride is used to encapsulate the copper wires on superhigh-density chips. That extra processing step became necessary because copper molecules from the wires connecting superdense transistors sometimes diffuse through the normal insulation layers, causing shorts.

Thinning barriers

A semiconductor like metal nitride works as a barrier layer to separate copper from insulation layers. But as chips continue to shrink that barrier will have to shrink too, eventually reaching the limit of only a molecule of two in thickness, thereby again risking the chance of shorts.

"In the future, chipmakers will have to go to barrier layers that are only a molecule or two thick?any thicker, and there won't be enough copper left inside the wire to efficiently transfer signals," Muscat said. "Today we don't know how to deposit a layer one or two molecules thick that is uniform. It can't be two molecules thick in one place and 12 molecules thick elsewhere if it is going coat a feature that's 10 times deeper than it is wide."

To anticipate and fix this problem before semiconductor manufacturers have to face it, Muscat's team is devising new chemical formulations of nitride film. Current formulations don't "stick" to the copper, which doesn't matter at today's thicknesses. The formulas now being developed will not only stick to copper but will self-assemble into a uniform thickness of just a few molecules.

The group is also studying other barrier films that can isolate transistor gates in future ultrahigh-density chips. Silicon dioxide is most often used today to form gates, but next-generation gate materials will likely require barriers to discourage undesirable alloys from forming on them during high-temperature processing steps, Muscat said.

? R.Colin Johnson

EE Times

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